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2024-04-30drm/i915/dpio: Extract vlv_dpio_phy_regs.hdrm-intel-next-2024-04-30Ville Syrjälä6-298/+313
2024-04-30drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä4-202/+229
2024-04-30drm/i915/dpio: Clean up VLV/CHV DPIO PHY register definesVille Syrjälä2-176/+101
2024-04-30drm/i915/dpio: Rename a few CHV DPIO PHY registersVille Syrjälä3-24/+23
2024-04-30drm/i915/dpio: Give VLV DPIO group register a clearer nameVille Syrjälä2-62/+62
2024-04-30drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooksVille Syrjälä2-17/+11
2024-04-30drm/i915/dpio: s/pipe/ch/Ville Syrjälä1-24/+25
2024-04-30drm/i915/dpio: s/port/ch/Ville Syrjälä2-49/+49
2024-04-30drm/i915/dpio: Rename some variablesVille Syrjälä1-49/+48
2024-04-30drm/i915/dpio: Remove pointless variables from vlv/chv DPLL codeVille Syrjälä1-36/+28
2024-04-30drm/i915/dpio: Fix VLV DPIO PLL register dword numberingVille Syrjälä2-21/+21
2024-04-30drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/Ville Syrjälä2-2/+3
2024-04-30drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/Ville Syrjälä2-6/+6
2024-04-30drm/i915/dpio: Remove pointless VLV_PCS01_DW8 readVille Syrjälä1-1/+0
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C22Jani Nikula2-3/+3
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C21_C20Jani Nikula2-3/+3
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C12Jani Nikula2-3/+3
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C11_C10Jani Nikula2-3/+3
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C02Jani Nikula2-3/+3
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C01_C00Jani Nikula2-3/+3
2024-04-30drm/i915: pass dev_priv explicitly to PALETTEJani Nikula2-11/+20
2024-04-29drm/i915/display: split out intel_sprite_regs.h from i915_reg.hJani Nikula8-341/+357
2024-04-29drm/i915/display: split out intel_fbc_regs.h from i915_reg.hJani Nikula6-123/+125
2024-04-29drm/i915/color: move palette registers to intel_color_regs.hJani Nikula2-31/+29
2024-04-29drm/i915/audio: move LPE audio regs to intel_audio_regs.hJani Nikula3-17/+17
2024-04-25drm/{i915, xe}: Implement fbdev emulation as in-kernel clientdrm-intel-next-2024-04-26Thomas Zimmermann5-140/+80
2024-04-25drm/{i915,xe}: Implement fbdev client callbacksThomas Zimmermann5-49/+25
2024-04-25drm/{i915,xe}: Unregister in-kernel clientsThomas Zimmermann2-0/+4
2024-04-25drm/i915: Initialize fbdev DRM client with callback functionsThomas Zimmermann1-4/+39
2024-04-25drm/i915: Move fbdev functionsThomas Zimmermann1-77/+77
2024-04-25drm/client: Export drm_client_dev_unregister()Thomas Zimmermann1-0/+13
2024-04-25drm/i915: pass dev_priv to _MMIO_PIPE2, _MMIO_TRANS2, _MMIO_CURSOR2Jani Nikula4-128/+128
2024-04-25drm/i915: convert _MMIO_PIPE3()/_MMIO_PORT3() to accept baseJani Nikula2-40/+44
2024-04-23drm/i915/dsi: pass display to register macros instead of implicit variabledrm-intel-next-2024-04-24Jani Nikula4-342/+349
2024-04-23drm/i915/dsi: unify connector/encoder type and name usageJani Nikula1-74/+60
2024-04-23drm/i915/dsi: add VLV_ prefix to VLV only register macrosJani Nikula2-5/+5
2024-04-23drm/i915/dsi: remove unused _MIPIA_AUTOPWG register definitionJani Nikula1-3/+0
2024-04-22drm/i915/display: move dmc_firmware_path to display paramsJani Nikula6-9/+6
2024-04-22drm/i915/dmc: change how to disable DMC firmware using module paramJani Nikula2-10/+24
2024-04-22drm/i915/dmc: split out per-platform firmware path selectionJani Nikula1-42/+54
2024-04-22drm/i915/dmc: improve firmware parse failure propagationJani Nikula1-17/+24
2024-04-22drm/i915/dmc: handle request_firmware() errors separatelyJani Nikula1-2/+9
2024-04-19drm/i915: Enable per-lane DP drive settings for bxt/glkVille Syrjälä1-1/+1
2024-04-19drm/i915/dpio: Program bxt/glk PHY TX registers per-laneVille Syrjälä1-13/+22
2024-04-19drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuffVille Syrjälä5-102/+102
2024-04-19drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setupVille Syrjälä1-9/+3
2024-04-19drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp()Ville Syrjälä1-22/+39
2024-04-19drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä8-262/+279
2024-04-19drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä5-35/+35
2024-04-19drm/i915/dpio: Clean up bxt/glk PHY registersVille Syrjälä2-59/+59
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-18 05:13:42 +0000