diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2016-12-13 13:10:59 +0200 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2016-12-14 15:18:52 +0200 |
| commit | 9eebfdbff2f857fbb7d730e338e3ad37b684bd5d (patch) | |
| tree | 48a9bd584e4f957a00dd13df414affcc9ebee5c2 /drivers/gpu/drm/i915/i915_gem_fence_reg.c | |
| parent | 2dd85aeb5bc99e3763dd192cdb95ff405a102c8a (diff) | |
drm/i915: simplify check for I915G/I945G in bit 6 swizzling detection
Commit c9c4b6f6c283 ("drm/i915: fix swizzle detection for gen3") added a
complicated check for I915G/I945G. Pineview and other gen3 devices match
IS_MOBILE() anyway. Simplify.
Cc: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1481627459-488-1-git-send-email-jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_fence_reg.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_fence_reg.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index 09193cfb5d8b..e03983973252 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -513,8 +513,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; } else if (IS_MOBILE(dev_priv) || - (IS_GEN3(dev_priv) && - !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv))) { + IS_I915G(dev_priv) || IS_I945G(dev_priv)) { uint32_t dcc; /* On 9xx chipsets, channel interleave by the CPU is |