| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-01-06 | [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dc... | Colin LeMahieu | 1 | -1/+2 |
| 2014-12-08 | [Hexagon] Adding xtype parity, min, minu, max, maxu instructions. | Colin LeMahieu | 1 | -0/+4 |
| 2014-12-05 | [Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combi... | Colin LeMahieu | 1 | -0/+1 |
| 2014-08-13 | Canonicalize header guards into a common format. | Benjamin Kramer | 1 | -2/+2 |
| 2014-06-27 | Make HexagonISelLowering not dependent upon a HexagonTargetMachine, | Eric Christopher | 1 | -2/+2 |
| 2014-06-10 | SelectionDAG: Expand SELECT_CC to SELECT + SETCC | Tom Stellard | 1 | -1/+0 |
| 2014-04-29 | [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final... | Craig Topper | 1 | -22/+21 |
| 2013-11-13 | SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too. | Juergen Ributzka | 1 | -2/+5 |
| 2013-08-06 | Refactor isInTailCallPosition handling | Tim Northover | 1 | -0/+2 |
| 2013-06-22 | The getRegForInlineAsmConstraint function should only accept MVT value types. | Chad Rosier | 1 | -1/+1 |
| 2013-05-25 | Track IR ordering of SelectionDAG nodes 2/4. | Andrew Trick | 1 | -3/+3 |
| 2013-05-18 | Add LLVMContext argument to getSetCCResultType | Matt Arsenault | 1 | -1/+1 |
| 2013-05-01 | Hexagon: Use multiclass for Jump instructions. | Jyotsna Verma | 1 | -1/+3 |
| 2013-04-20 | Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. | Tim Northover | 1 | -1/+0 |
| 2013-03-07 | Hexagon: Add support to lower block address. | Jyotsna Verma | 1 | -0/+2 |
| 2013-03-05 | reverting patch 176508. | Jyotsna Verma | 1 | -2/+0 |
| 2013-03-05 | Hexagon: Add support for lowering block address. | Jyotsna Verma | 1 | -0/+2 |
| 2013-02-04 | Hexagon: Add V4 combine instructions and some more Def Pats for V2. | Jyotsna Verma | 1 | -0/+2 |
| 2013-01-02 | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 1 | -1/+1 |
| 2012-12-04 | Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading... | Jyotsna Verma | 1 | -0/+9 |
| 2012-12-04 | Sort includes for all of the .h files under the 'lib' tree. These were | Chandler Carruth | 1 | -1/+1 |
| 2012-05-25 | Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall | Justin Holewinski | 1 | -7/+1 |
| 2012-05-10 | Hexagon V5 FP Support. | Sirish Pande | 1 | -0/+4 |
| 2012-04-23 | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth | 1 | -4/+0 |
| 2012-04-23 | Hexagon V5 (floating point) support. | Sirish Pande | 1 | -0/+4 |
| 2012-04-18 | This reverts a long string of commits to the Hexagon backend. These | Chandler Carruth | 1 | -4/+0 |
| 2012-04-16 | Hexagon V5 (Floating Point) Support. | Sirish Pande | 1 | -0/+4 |
| 2012-03-17 | Reorder includes in Target backends to following coding standards. Remove som... | Craig Topper | 1 | -1/+1 |
| 2012-02-28 | Re-commit r151623 with fix. Only issue special no-return calls if it's a dire... | Evan Cheng | 1 | -1/+1 |
| 2012-02-28 | Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre... | Daniel Dunbar | 1 | -1/+1 |
| 2012-02-28 | Some ARM implementaions, e.g. A-series, does return stack prediction. That is, | Evan Cheng | 1 | -1/+1 |
| 2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 1 | -1/+1 |
| 2011-12-12 | Hexagon backend support | Tony Linthicum | 1 | -0/+162 |
