diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2012-09-11 15:24:32 -0400 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-09-14 16:00:08 +0000 |
| commit | 9e6fa84e89655092154c5fb60496039b49bf0497 (patch) | |
| tree | 7e0d09b397d1f44c0cc9abdcb814cebea17bf3c5 /lib/Target/AMDGPU/AMDGPUISelLowering.h | |
| parent | 818196e07a7fa9f5962151c7bce4579d7a02a055 (diff) | |
R600: Fix lowering of vbuildr600-review-v10
Some of the old AMDIL code was hard-coding subreg indices when creating
the VBUILD node, which was making it difficult to match the
vector_insert patterns.
Diffstat (limited to 'lib/Target/AMDGPU/AMDGPUISelLowering.h')
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUISelLowering.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.h b/lib/Target/AMDGPU/AMDGPUISelLowering.h index 4c100da9690..a6d2a50d11b 100644 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -90,7 +90,6 @@ private: SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; @@ -105,7 +104,6 @@ enum // AMDIL ISD Opcodes FIRST_NUMBER = ISD::BUILTIN_OP_END, MAD, // 32bit Fused Multiply Add instruction - VBUILD, // scalar to vector mov instruction CALL, // Function call based on a single integer UMUL, // 32bit unsigned multiplication DIV_INF, // Divide with infinity returned on zero divisor |