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authorTom Stellard <thomas.stellard@amd.com>2013-10-10 00:06:31 -0400
committerTom Stellard <thomas.stellard@amd.com>2013-10-10 00:06:31 -0400
commite14ac440560f07f5c46d477c16984550b9065268 (patch)
tree268db6317e00468ef44dc161dd58912fecd0a8bb
parent915f29e7245a5bdb8a3209e9715540b60234f5a5 (diff)
-rw-r--r--lib/Target/R600/SIInstrInfo.cpp18
1 files changed, 17 insertions, 1 deletions
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index 3b816bb2367..21510bf54c5 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -530,7 +530,23 @@ bool SIInstrInfo::moveToVALU(MachineInstr &MI) const {
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
// Use the new VALU Opcode;
- MI.setDesc(get(NewOpcode));
+ const MCInstrDesc &NewDesc = get(NewOpcode);
+ MI.setDesc(NewDesc);
+
+ // Add the implict and explicit register definitions
+ if (NewDesc.ImplicitUses) {
+ for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
+ MI.addOperand(MachineOperand::CreateReg(NewDesc.ImplicitUses[i],
+ false, true));
+ }
+ }
+
+ if (NewDesc.ImplicitDefs) {
+ for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
+ MI.addOperand(MachineOperand::CreateReg(NewDesc.ImplicitDefs[i],
+ true, true));
+ }
+ }
// Update the destination register class
const TargetRegisterClass *NewDstRC = getOpRegClass(MI, 0);