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author | Tom Stellard <thomas.stellard@amd.com> | 2014-11-25 15:21:45 +0000 |
---|---|---|
committer | Tom Stellard <thomas.stellard@amd.com> | 2014-12-10 02:12:51 +0000 |
commit | 6b45dda934773f42c144ba982d15f356f0de011e (patch) | |
tree | 4238d407af438f40c21efa55bd1fc32744c158d5 | |
parent | 3c01a870e48499b387ad65cda61adaabb4b0a00e (diff) |
ScheduleDAGInstrs: Consider sub-registers when computing vreg def dependenciesmi-sched-experimental
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index d8d8422f0ed..6cdef8200b7 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -375,11 +375,12 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { const MachineInstr *MI = SU->getInstr(); unsigned Reg = MI->getOperand(OperIdx).getReg(); + unsigned SubReg = MI->getOperand(OperIdx).getSubReg(); // Singly defined vregs do not have output/anti dependencies. // The current operand is a def, so we have at least one. // Check here if there are any others... - if (MRI.hasOneDef(Reg)) + if (MRI.hasOneDef(Reg, SubReg)) return; // Add output dependence to the next nearest def of this vreg. |