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2010-10-05r600g: simplify block relocationHEADmasterJerome Glisse3-12/+9
Since flush rework there could be only one relocation per register in a block. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05r600g: use dirty list to track dirty blocksBas Nieuwenhuizen4-8/+33
Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty.
2010-10-05docs: added news item for 7.9 releaseIan Romanick1-1/+9
Also fix link to release notes in 7.9-rc1 news item.
2010-10-05docs: Import news updates from 7.9 branchIan Romanick1-0/+8
Partially cherry-picked from commit 61653b488da76ee1ca4f77363e222d3b717dd865
2010-10-05docs: Update mailing lines from sf.net to freedesktop.orgIan Romanick1-3/+4
(cherry picked from commit c19bc5de961fe5e1f8a17131bcfae3dbcccaca29)
2010-10-05docs: download.html does not need to be updated for each releaseIan Romanick1-1/+1
(cherry picked from commit 41e371e351cc4c77b2b20a545af2dfa2dab253d7)
2010-10-05docs: Import 7.8.x release notes from 7.8 branch.Ian Romanick3-3/+186
2010-10-05docs: Import 7.9 release notes from 7.9 branch.Ian Romanick1-2/+9
2010-10-05nv50: fix always true conditional in shader optimizationNicolas Kaiser1-1/+1
2010-10-05r600g: improve bo flushingJerome Glisse4-822/+825
Flush read cache before writting register. Track flushing inside of a same cs and avoid reflushing same bo if not necessary. Allmost properly force flush if bo rendered too and then use as a texture in same cs (missing pipeline flush dunno if it's needed or not). Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05r600g: store reloc information in bo structureJerome Glisse2-23/+16
Allow fast lookup of relocation information & id which was a CPU time consumming operation. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-05pb: fix numDelayed accountingDave Airlie1-0/+1
we weren't decreasing when removing from the list.
2010-10-05r600g: avoid unneeded bo waitDave Airlie1-1/+5
if we know the bo has gone not busy, no need to add another bo wait thanks to Andre (taiu) on irc for pointing this out.
2010-10-05r600g: drop use_mem_constant.Dave Airlie9-14/+3
since we plan on using dx10 constant buffers everywhere.
2010-10-05r600g: drop mman allocatorDave Airlie3-8/+1
we don't use this since constant buffers are now being used on all gpus.
2010-10-05r600g: add bo busy backoff.Dave Airlie2-0/+15
When we go to do a lot of bos in one draw like constant bufs we need to avoid bouncing off the busy ioctl, this mitigates by backing off on busy bos for a short amount of times.
2010-10-05pb: don't keep checking buffers after first busyDave Airlie1-13/+19
If we assume busy buffers are added to the list in order its unlikely we'd fine one after the first busy one that isn't busy.
2010-10-05r600g: add bo fenced list.Dave Airlie3-0/+43
this just keeps a list of bos submitted together, and uses them to decide bo busy state for the whole group.
2010-10-04swrast: fix choose_depth_texture_level() to respect mipmap filtering stateBrian Paul1-5/+10
NOTE: this is a candidate for the 7.9 branch.
2010-10-05r300g: fix microtiling for 16-bits-per-channel formatsMarek Olšák1-3/+3
These texture formats (like R16G16B16A16_UNORM) were untested until now because st/mesa doesn't use them. I am testing this with a hacked st/mesa here.
2010-10-05update release notes for GalliumMarek Olšák1-4/+19
I am trying to be exhaustive, but still I might have missed tons of other changes to Gallium. (cherry picked from commit 968a9ec76eadf55e8b58171884e1175d7b8cf59a) Conflicts: docs/relnotes-7.9.html
2010-10-04docs: Add list of bugs fixed in 7.9Ian Romanick1-0/+52
2010-10-04i965: Add support for gen6 FB writes to the new FS.Eric Anholt2-3/+22
This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
2010-10-04i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.Eric Anholt1-1/+1
It instead sensibly appears in the src0 slot.
2010-10-04i965: Add initial folding of constants into operand immediate slots.Eric Anholt1-0/+90
We could try to detect this in expression handling and do it proactively there, but it seems like less logic to do it in one optional pass at the end.
2010-10-04i965: Add trivial dead code elimination in the new FS backend.Eric Anholt1-2/+50
The glsl core should be handling most dead code issues for us, but we generate some things in codegen that may not get used, like the 1/w value or pixel deltas. It seems a lot easier this way than trying to work out up front whether we're going to use those values or not.
2010-10-04i965: Be more conservative on live interval calculation.Eric Anholt1-3/+11
This also means that our intervals now highlight dead code.
2010-10-04r600g: Fix SCons build.Vinson Lee1-1/+1
2010-10-04r600g: remove dead label & fix indentationJerome Glisse1-11/+9
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04r600g: rename radeon_ws_bo to r600_boJerome Glisse2-1/+1
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04r600g: use r600_bo for relocation argument, simplify codeJerome Glisse4-19/+29
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04r600g: allow r600_bo to be a sub allocation of a big boJerome Glisse6-28/+37
Add bo offset everywhere needed if r600_bo is ever a sub bo of a bigger bo. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04r600g: rename radeon_ws_bo to r600_boJerome Glisse12-86/+86
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-04nvfx: Pair os_malloc_aligned() with os_free_aligned().Krzysztof Smiechowicz1-1/+1
From AROS.
2010-10-04r600g: TODO domain managementDave Airlie1-2/+2
no wonder it was slow, the code is deliberately forcing stuff into GTT, we used to have domain management but it seems to have disappeared.
2010-10-04r600g: fix wwarning in bo_map functionDave Airlie1-0/+1
2010-10-04r600g: the code to check whether a new vertex shader is needed was wrongDave Airlie1-1/+3
this code was memcmp'ing two structs, but refcounting one of them afterwards, so any subsequent memcmp was never going to work. again this stops unnecessary uploads of vertex program,
2010-10-04r600g: break out of search for reloc bo after finding it.Dave Airlie1-0/+1
this function was taking quite a lot of pointless CPU.
2010-10-03i965: Fix glean/texSwizzle regression in previous commit.Eric Anholt1-18/+18
Easy enough patch, who needs a full test run. Oh, that's right. Me.
2010-10-02i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.Eric Anholt1-1/+32
The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't apply to shadow compares, which always return an intensity value. The texture swizzles can do the job for us. Fixes: glsl1-shadow2D(): 1 glsl1-shadow2D(): 3
2010-10-02i965: Add support for EXT_texture_swizzle to the new FS backend.Eric Anholt1-0/+21
2010-10-02r300g: add support for L8A8 colorbuffersMarek Olšák1-0/+3
Blending with DST_ALPHA is undefined. SRC_ALPHA works, though. I bet some other formats have similar limitations too.
2010-10-02r300g: add support for R8G8 colorbuffersMarek Olšák1-1/+11
The hw swizzles have been obtained by a brute force approach, and only C0 and C2 are stored in UV88, the other channels are ignored. R16G16 is going to be a lot trickier.
2010-10-02mesa/st: initial attempt at RG support for gallium driversDave Airlie4-1/+93
passes all piglit RG tests with softpipe.
2010-10-01i965: Fix incorrect batchbuffer size in gen6 clip state command.Kenneth Graunke1-1/+0
FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
2010-10-01i965: Don't try to emit code if we failed register allocation.Eric Anholt1-1/+2
2010-10-01i965: Fix off-by-ones in handling the last members of register classes.Eric Anholt1-5/+5
Luckily, one of them would result in failing out register allocation when the other bugs were encountered. Applies to glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still fails register allocation, but now legitimately.
2010-10-01i965: Add a sanity check for register allocation sizes.Eric Anholt1-0/+5
2010-10-01i965: When producing a single channel swizzle, don't make a temporary.Eric Anholt1-0/+5
This quickly cuts 8% of the instructions in my glsl demo.
2010-10-01i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.Eric Anholt1-12/+43
By doing so using the register allocator now, we avoid wasting a register to make the alignment happen.
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