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path: root/i965_defines.h
AgeCommit message (Expand)AuthorFilesLines
2011-08-22Moved files around.Gwenole Beauchesne1-708/+0
2011-06-14i965_drv_video: fix GPU hang issue when decoding field coded MPEG2 picture.Xiang, Haihao1-0/+4
2011-06-10i965_drv_video: encode on IvybridgeXiang, Haihao1-0/+1
2011-05-25i965_drv_video: rendering for IvybridgeXiang, Haihao1-4/+133
2011-05-25i965_drv_video: VC1 decoding on IvybridgeXiang, Haihao1-0/+3
2011-05-25i965_drv_video: H.264 & MPEG2 decoding on IvybridgeXiang, Haihao1-0/+17
2011-05-25i965_drv_video: Ivybridge PCI IDsXiang, Haihao1-1/+2
2011-05-16i965_drv_video: clean up batchbuffer interfaceXiang, Haihao1-2/+0
2011-04-07i965_drv_vidoe: Encoder on Sandy BridgeZhou Chang1-0/+9
2011-03-11i965_drv_video: rendere I420/YV12 surface on SandyBridgeXiang, Haihao1-0/+5
2011-03-10i965_drv_video: deinterlacing & scaling on SandyBridgeXiang, Haihao1-0/+7
2011-01-26i965_drv_video: VC-1 on SandybridgeXiang, Haihao1-0/+6
2010-12-06i965_drv_video: add support for mpeg2 decoding on SandybridgeXiang, Haihao1-0/+5
2010-12-06i965_drv_video/render: rendering for SandybridgeXiang, Haihao1-0/+96
2010-12-06i965_drv_video: H.264 decoding on SandybridgeXiang, Haihao1-2/+3
2010-12-06i965_drv_video: MACROs for MFX on SandybridgeXiang, Haihao1-0/+39
2010-12-06i965_drv_video: PCI IDs and new MI_FLUSH_DW command for SandybridgeXiang, Haihao1-1/+3
2010-09-15i965_drv_video: deinterlacing & scalingXiang, Haihao1-0/+23
2010-04-06i965_drv_video: initialize depth bufferZou nan hai1-0/+3
2010-03-26i965_drv_video: add support for H264 on Clarkdale/ArrandaleXiang, Haihao1-1/+34
2009-11-18fix upload of the subpicture palette.Gwenole Beauchesne1-1/+1
2009-07-27i965_drv_video: Eanble VAAPI on IGDNGXiang, Haihao1-1/+2
2009-07-02Apply the patch from Nanhai to support MPEG2 VLD on Intel integrated G45 grap...Austin Yuan1-0/+325