Host: Add host support for CN400, CN700, P4M890, K8M890 and VX800.

Now the full range of hardware has its first prerequisite fulfilled:
host support.

Direct FB access for K8M890 is not enabled yet.

4 files changed, 208 insertions, 39 deletions

diff --git a/src/via_driver.c b/src/via_driver.c
index f1be004..5cfb337 100644
--- a/src/via_driver.c
+++ b/src/via_driver.c
@@ -768,7 +768,8 @@ ViaScratchGet(ScrnInfoPtr pScrn)
      *  8: DDR2 133Mhz (DDR2 533)
      *  9: DDR2 166Mhz (DDR2 667)
      *  A: DDR2 200Mhz (DDR2 800)
-     *  B and above: Unknown.
+     *  B: DDR2 233Mhz (DDR2 1066)
+     *  C: and above: Unknown.
      */
     /* SDR won't happen, assume badly set up register. */
     if ((tmp < 0x03) || (tmp > 0x0A)) {
diff --git a/src/via_driver.h b/src/via_driver.h
index 8466c53..ab6cee2 100644
--- a/src/via_driver.h
+++ b/src/via_driver.h
@@ -84,15 +84,16 @@ typedef struct pci_device *pciVideoPtr;
 #define VIA_DEVICE_DVI   0x08
 
 /* For pVia->MemClk */
-#define VIA_MEM_DDR_200  0x00
-#define VIA_MEM_DDR_266  0x01
-#define VIA_MEM_DDR_333  0x02
-#define VIA_MEM_DDR_400  0x03
-#define VIA_MEM_DDR2_400 0x04
-#define VIA_MEM_DDR2_533 0x05
-#define VIA_MEM_DDR2_667 0x06
-#define VIA_MEM_DDR2_800 0x07
-#define VIA_MEM_END      0x08
+#define VIA_MEM_DDR_200   0x00
+#define VIA_MEM_DDR_266   0x01
+#define VIA_MEM_DDR_333   0x02
+#define VIA_MEM_DDR_400   0x03
+#define VIA_MEM_DDR2_400  0x04
+#define VIA_MEM_DDR2_533  0x05
+#define VIA_MEM_DDR2_667  0x06
+#define VIA_MEM_DDR2_800  0x07
+#define VIA_MEM_DDR2_1066 0x08
+#define VIA_MEM_END      0x09
 #define VIA_MEM_NONE     0xFF
 
 /* For Scratch->TVStandard */
diff --git a/src/via_host.c b/src/via_host.c
index c5162f8..cccbbe8 100644
--- a/src/via_host.c
+++ b/src/via_host.c
@@ -103,8 +103,13 @@ ViaHostIdentify(ScrnInfoPtr pScrn)
 	{0x3205, VIA_HOST_KM400 , "KM400/KN400"},
 	{0x0296, VIA_HOST_P4M800, "P4M800"},
 	{0x0204, VIA_HOST_K8M800, "K8M800/K8N800"},
-	{0x0324, VIA_HOST_CX700,  "CX700"},
+	{0x0259, VIA_HOST_CN400,  "CN400/PM800/PM880"},
+	{0x0314, VIA_HOST_CN700,  "CN700/VN800/P4M800CE/P4M800Pro"},
+	{0x0324, VIA_HOST_CX700,  "CX700/VX700"},
+	{0x0290, VIA_HOST_K8M890, "K8M890"},
+	{0x0327, VIA_HOST_P4M890, "P4M890"},
 	{0x0364, VIA_HOST_P4M900, "P4M900/VN896/CN896"},
+	{0x0353, VIA_HOST_VX800,  "VX800"},
 	{0xFFFF, 0x00, NULL}
     };
     VIAPtr pVia = VIAPTR(pScrn);
@@ -399,11 +404,72 @@ P4M800RAMTypeGet(ScrnInfoPtr pScrn)
 }
 
 /*
- * Suited for P4M800Pro and P4M900.
+ * Similar to P4M800, but not quite.
+ */
+static CARD8
+CN400RAMTypeGet(ScrnInfoPtr pScrn)
+{
+    CARD8 FSB, FSBtoRAM;
+    int Freq;
+
+    /* 0x2259 */
+    PCIREADBYTE(PCIDEVFROMPOS(0, 0, 2), 0x54, &FSB);
+    switch(FSB >> 5) {
+    case 0:
+	Freq = 3; /* x33Mhz  = 100Mhz */
+	break;
+    case 1:
+	Freq = 4; /* 133Mhz */
+	break;
+    case 3:
+	Freq = 5; /* 166Mhz */
+	break;
+    case 2:
+	Freq = 6; /* 200Mhz */
+	break;
+    case 4:
+	Freq = 7; /* 233Mhz */
+	break;
+    default:
+	xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "%s: Unhandled FSB: %d\n",
+		   __func__, FSB);
+	return VIA_MEM_NONE;
+    }
+
+    /* FSB to RAM timing from 0x3259 */
+    PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0x68, &FSBtoRAM);
+    FSBtoRAM &= 0x0F;
+
+    if (FSBtoRAM & 0x01)
+	Freq += 1 + (FSBtoRAM >> 2);
+    else if (FSBtoRAM & 0x02)
+	Freq -= 1 + (FSBtoRAM >> 2);
+
+    switch (Freq) {
+    case 0x03:
+	return VIA_MEM_DDR_200;
+    case 0x04:
+	return VIA_MEM_DDR_266;
+    case 0x05:
+	return VIA_MEM_DDR_333;
+    case 0x06:
+	return VIA_MEM_DDR_400;
+    default:
+	break;
+    }
+
+    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+	       "%s: Illegal RAM type: FSB %1d, FSBtoRAM, %1d\n",
+	       __func__, FSB, FSBtoRAM);
+    return VIA_MEM_NONE;
+}
+
+/*
+ * Suited for CN700/VX800/P4M800CE/P4M800Pro, P4M890, P4M900/CN896, VX800.
  *
  */
 static CARD8
-P4M800ProRAMTypeGet(ScrnInfoPtr pScrn)
+CN700RAMTypeGet(ScrnInfoPtr pScrn)
 {
     CARD8 tmp;
 
@@ -431,41 +497,110 @@ P4M800ProRAMTypeGet(ScrnInfoPtr pScrn)
 }
 
 /*
- * Simply poke the K8 DRAM controller.
+ * From the different AMD CPU bios and kernel developers guides.
+ * AMD is nice like that :)
  */
 static CARD8
-AMDK8RAMTypeGet(ScrnInfoPtr pScrn)
+AMDRAMTypeGet(ScrnInfoPtr pScrn)
 {
     PCIDEVVAR Dev;
     CARD8 tmp;
 
     VIAFUNC(pScrn->scrnIndex);
 
-    /* AMD K8 DRAM Controller */
+    /* AMD 0Fh DRAM Controller */
     Dev = PCIDEVFROMIDS(0x1022, 0x1102);
-    if (!PCIDEVFOUND(Dev)) {
-	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		   "%s: Unable to find AMD K8 DRAM Controller.\n", __func__);
-	return VIA_MEM_NONE;
+    if (PCIDEVFOUND(Dev)) {
+	PCIREADBYTE(Dev, 0x96, &tmp);
+	tmp >>= 4;
+	tmp &= 0x07;
+	switch(tmp) {
+	case 0x00:
+	    return VIA_MEM_DDR_200;
+	case 0x02:
+	    return VIA_MEM_DDR_266;
+	case 0x05:
+	    return VIA_MEM_DDR_333;
+	case 0x07:
+	    return VIA_MEM_DDR_400;
+	default:
+	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		       "%s: Unhandled DRAM MemClk: 0x%02X.\n", __func__, tmp);
+	    return VIA_MEM_NONE;
+	}
     }
 
-    PCIREADBYTE(Dev, 0x96, &tmp);
-    tmp >>= 4;
-    tmp &= 0x07;
-    switch(tmp) {
-    case 0x00:
-	return VIA_MEM_DDR_200;
-    case 0x02:
-	return VIA_MEM_DDR_266;
-    case 0x05:
-	return VIA_MEM_DDR_333;
-    case 0x07:
-	return VIA_MEM_DDR_400;
-    default:
-	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		   "%s: Unhandled DRAM MemClk: 0x%02X.\n", __func__, tmp);
-	return VIA_MEM_NONE;
+    /* AMD 10h DRAM Controller */
+    Dev = PCIDEVFROMIDS(0x1022, 0x1202);
+    if (PCIDEVFOUND(Dev)) {
+	CARD8 type;
+
+	PCIREADBYTE(Dev, 0x94, &tmp);
+	PCIREADBYTE(Dev, 0x95, &type);
+
+	if (type & 0x01) { /* DDR3 */
+#ifndef NO_DDR3_YET
+	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		       "%s: DDR3 is not supported yet.\n", __func__);
+	    return VIA_MEM_NONE;
+#else
+	    switch(tmp & 0x07) {
+	    case 0x03:
+		return VIA_MEM_DDR3_800;
+	    case 0x04:
+		return VIA_MEM_DDR3_1066;
+	    case 0x05:
+		return VIA_MEM_DDR3_1333;
+	    case 0x06:
+		return VIA_MEM_DDR3_1600;
+	    default:
+		xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+			   "%s: Unhandled DRAM MemClk: 0x%02X.\n", __func__, tmp);
+		return VIA_MEM_NONE;
+	    }
+#endif
+	} else { /* DDR2 */
+	    switch(tmp & 0x07) {
+	    case 0x00:
+		return VIA_MEM_DDR2_400;
+	    case 0x01:
+		return VIA_MEM_DDR2_533;
+	    case 0x02:
+		return VIA_MEM_DDR2_667;
+	    case 0x03:
+		return VIA_MEM_DDR2_800;
+	    case 0x04:
+		return VIA_MEM_DDR2_1066;
+	    default:
+		xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+			   "%s: Unhandled DRAM MemClk: 0x%02X.\n", __func__, tmp);
+		return VIA_MEM_NONE;
+	    }
+	}
+    }
+
+    /* AMD 11h DRAM Controller */
+    Dev = PCIDEVFROMIDS(0x1022, 0x1302);
+    if (PCIDEVFOUND(Dev)) {
+	PCIREADBYTE(Dev, 0x94, &tmp);
+
+	switch(tmp & 0x07) {
+	case 0x01:
+	    return VIA_MEM_DDR2_533;
+	case 0x02:
+	    return VIA_MEM_DDR2_667;
+	case 0x03:
+	    return VIA_MEM_DDR2_800;
+	default:
+	    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		       "%s: Unhandled DRAM MemClk: 0x%02X.\n", __func__, tmp);
+	    return VIA_MEM_NONE;
+	}
     }
+
+    xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+	       "%s: Unable to find an AMD CPU DRAM Controller.\n", __func__);
+    return VIA_MEM_NONE;
 }
 
 /*
@@ -532,7 +667,8 @@ ViaMemoryInfoString(CARD8 MemType)
 	{ VIA_MEM_DDR2_400, "100MHz DDR2 - PC2-3200"},
 	{ VIA_MEM_DDR2_533, "133MHz DDR2 - PC2-4200"},
 	{ VIA_MEM_DDR2_667, "166MHz DDR2 - PC2-5300"},
-	{ VIA_MEM_DDR2_800, "200MHz DDR2 - PC2-6400"}
+	{ VIA_MEM_DDR2_800, "200MHz DDR2 - PC2-6400"},
+	{ VIA_MEM_DDR2_1066, "266MHz DDR2 - PC2-8500"},
     };
     int i;
 
@@ -575,17 +711,38 @@ ViaFBInit(ScrnInfoPtr pScrn)
     case VIA_HOST_K8M800:
 	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
 	pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 1024;
-	pVia->MemType = AMDK8RAMTypeGet(pScrn);
+	pVia->MemType = AMDRAMTypeGet(pScrn);
+	break;
+    case VIA_HOST_CN400:
+	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
+	pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 1024;
+	pVia->MemType = CN400RAMTypeGet(pScrn);
+	break;
+    case VIA_HOST_CN700:
+	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
+	pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 1024;
+	pVia->MemType = CN700RAMTypeGet(pScrn);
 	break;
     case VIA_HOST_CX700:
 	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
         pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 4096;
         pVia->MemType = CX700RAMTypeGet(pScrn);
         break;
+    case VIA_HOST_K8M890:
+	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
+        pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 4096;
+        pVia->MemType = AMDRAMTypeGet(pScrn);
+        break;
+    case VIA_HOST_P4M890:
+	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
+        pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 1024;
+        pVia->MemType = CN700RAMTypeGet(pScrn);
+        break;
     case VIA_HOST_P4M900:
+    case VIA_HOST_VX800:
 	PCIREADBYTE(PCIDEVFROMPOS(0, 0, 3), 0xA1, &tmp);
 	pScrn->videoRam = (1 << ((tmp & 0x70) >> 4)) * 4096;
-	pVia->MemType = P4M800ProRAMTypeGet(pScrn);
+	pVia->MemType = CN700RAMTypeGet(pScrn);
 	break;
     default:
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@@ -665,8 +822,12 @@ ViaFBBaseGet(ScrnInfoPtr pScrn)
 	}
 	break;
     case VIA_HOST_P4M800:
+    case VIA_HOST_CN400:
+    case VIA_HOST_CN700:
     case VIA_HOST_CX700:
+    case VIA_HOST_P4M890:
     case VIA_HOST_P4M900:
+    case VIA_HOST_VX800:
 	{
 	    CARD16 tmp;
 
@@ -675,6 +836,7 @@ ViaFBBaseGet(ScrnInfoPtr pScrn)
 		pVia->FrameBufferBase = (tmp & 0xFFE) << 20;
 	}
 	break;
+    case VIA_HOST_K8M890: /* i would need to get my hands on one first */
     default:
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
 		   "%s: Unhandled HostBridge.\n", __func__);
diff --git a/src/via_id.h b/src/via_id.h
index 64cbbb1..7acd773 100644
--- a/src/via_id.h
+++ b/src/via_id.h
@@ -87,8 +87,13 @@ enum VIAHostTags {
     VIA_HOST_KM400,
     VIA_HOST_P4M800,
     VIA_HOST_K8M800,
+    VIA_HOST_CN400,
+    VIA_HOST_CN700,
     VIA_HOST_CX700,
+    VIA_HOST_K8M890,
+    VIA_HOST_P4M890,
     VIA_HOST_P4M900,
+    VIA_HOST_VX800,
     VIA_HOST_LAST
 };