diff options
| author | Luc Verhaegen <libv@skynet.be> | 2009-04-22 12:02:25 +0200 |
|---|---|---|
| committer | Luc Verhaegen <libv@skynet.be> | 2009-04-22 12:02:25 +0200 |
| commit | 32d4e0a49bb2c419ab1a48407af0e6bfb449c0bd (patch) | |
| tree | b2ad6e394a8c20583e4c845f8b0ac13400f286a2 | |
| parent | a10502339ef1ace0881f668e8327be82b7acc0b2 (diff) | |
PLL: VT3122 generation: further optimise routine.
Move checking for internal frequency limit to the outer loop.
| -rw-r--r-- | src/via_crtc.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/via_crtc.c b/src/via_crtc.c index 9f74301..6892197 100644 --- a/src/via_crtc.c +++ b/src/via_crtc.c @@ -59,6 +59,10 @@ VT3122PLLGenerate(struct ViaCrtc *Crtc, int Clock) VIAFUNC(Crtc); for (Shift = 0; Shift < 4; Shift++) { + /* limit internal frequency to [20:750]MHz */ + if (((Clock << Shift) < 20000) || ((Clock << Shift) > 750000)) + continue; + for (Divider = 2; Divider < 26; Divider++) { for (RoundUp = 0; RoundUp < 2; RoundUp++) { if (RoundUp) @@ -66,15 +70,9 @@ VT3122PLLGenerate(struct ViaCrtc *Crtc, int Clock) else Multiplier = ((Clock * Divider) << Shift) / 14318; - if (Divider == 2) { - if (Multiplier > 0x6C) - continue; - } else { - if (Multiplier > 0x80) - continue; - } + if (Multiplier > 0x80) + continue; - /* painstakingly retrieved limit */ if (Divider > 11) /* 9, 10, 11 should never be hit */ if (Multiplier < (8 * (Divider - 9) - 1)) continue; |