diff options
author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2015-04-23 20:26:21 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2015-04-23 20:26:21 +0000 |
commit | ab740d1e40744b0c2bb4ce81de663022700bd1b3 (patch) | |
tree | a5992d2cf307a45051d9ab890481e2a7d45f1f54 | |
parent | 50b9e7f7d4ba3051387e3dd5dee38aa3e5bda675 (diff) |
[Hexagon] Fix compiler warnings in release build
Patch by Aditya Nandakumar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235635 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Hexagon/HexagonCopyToCombine.cpp | 2 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonFrameLowering.cpp | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 832f16fe03..1d6455c66f 100644 --- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -170,6 +170,8 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI, MachineInstr *LowRegInst) { unsigned HiOpc = HighRegInst->getOpcode(); unsigned LoOpc = LowRegInst->getOpcode(); + (void)HiOpc; // Fix compiler warning + (void)LoOpc; // Fix compiler warning assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) && (LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) && "Assume individual instructions are of a combinable type"); diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index 56f670ccf0..c701d2567e 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -580,6 +580,7 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const { // Handle EH_RETURN. if (RetOpc == Hexagon::EH_RETURN_JMPR) { MachineOperand &OffsetReg = RetI->getOperand(0); + (void)OffsetReg; // Silence compiler warning. assert(OffsetReg.isReg() && "Offset should be in register!"); BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::L2_deallocframe)); BuildMI(MBB, InsertPt, DL, HII.get(Hexagon::A2_add), SP) @@ -818,6 +819,7 @@ void HexagonFrameLowering::eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { MachineInstr &MI = *I; unsigned Opc = MI.getOpcode(); + (void)Opc; // Silence compiler warning. assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) && "Cannot handle this call frame pseudo instruction"); MBB.erase(I); @@ -993,7 +995,7 @@ void HexagonFrameLowering::processFunctionBeforeCalleeSavedScan( #ifndef NDEBUG -void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { +static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { dbgs() << '{'; for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { unsigned R = x; @@ -1007,6 +1009,7 @@ void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const { const Function &F = *MF.getFunction(); + (void)F; // Silence compiler warning. DEBUG(dbgs() << LLVM_FUNCTION_NAME << " on " << F.getName() << '\n'); MachineFrameInfo *MFI = MF.getFrameInfo(); BitVector SRegs(Hexagon::NUM_TARGET_REGS); |