index
:
~cwabbott0/mesa
cwabbott-lima
cwabbott-lima-2
glsl-to-nir-builder
i965-fp64
i965-fp64-v2
i965-fp64-v3
i965-payload-interference
i965-sched
i965-sched-conservative
i965-sched-conservative-v2
i965-sched-test
i965-sched-v2
i965-sched-v3
i965-use-ssa
i965-use-ssa-v2
ir3-sched
jenkins
master
nir-cf-insert-instr
nir-control-flow-mod
nir-cse-hash
nir-cse-hash-v2
nir-dead-cf-v2
nir-dead-cf-v3
nir-dead-cf-v4
nir-dead-cf-v5
nir-deref-instr
nir-divergence
nir-divergence-v2
nir-divergence-v3
nir-divergence-v4
nir-docs
nir-equality-saturation
nir-factor-phis
nir-foreach-block-rewrite
nir-foreach-block-rewrite-v2
nir-foreach-ssa-src
nir-gvn
nir-gvn-v2
nir-opcodes-cleanup
nir-opcodes-cleanup-v2
nir-opt-remove-phis
nir-reassociate-consts
nir-review-v1
nir-serialize
nir-v1.0.1
nir-value-range
nir-vec4-out-of-ssa
nir-vectorize
nir-worklist
radv-amd-shader-ballot
radv-anv-64bit-fixes
radv-doom-exts
radv-rewrite-vars
radv-shader-ballot
radv-shader-ballot-v3
radv-shader-ballot-v4
random-fp64-fixes
shader-time-hacks
test-compressed-wa
test-fp64-compressed-wa
ue4
wip/nir-vtn
Connor's silly Mesa stuff.
UNKNOWN
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2018-03-02
lima/gpir: Rework the scheduler
cwabbott-lima-2
Connor Abbott
1
-146
/
+316
2018-02-28
lima/gpir: Fix some bugs in instruction handling
Connor Abbott
1
-1
/
+13
2018-01-11
lima: remove unneccesary debug prints
Connor Abbott
1
-10
/
+0
2018-01-11
lima: make the cmdline compiler compile again
Connor Abbott
6
-12
/
+127
2018-01-11
Revert "lima: remove the stand alone compiler"
Connor Abbott
2
-0
/
+249
2018-01-11
lima: submit de-reference bos even syscall fail
Qiang Yu
1
-3
/
+2
2018-01-11
lima: submit reference added bo
Qiang Yu
2
-6
/
+16
2018-01-11
lima: drop the layer_stride in lima_resource
Qiang Yu
2
-3
/
+0
2018-01-11
lima: lima_resource_from_handle check bo alignment
Qiang Yu
1
-1
/
+16
2018-01-11
lima: really merge libdrm functions into mesa
Qiang Yu
20
-804
/
+662
2018-01-10
lima: fix change pp uniform for two draws in the same frame
Qiang Yu
2
-13
/
+22
2018-01-09
lima: pp uniform buffer update doesn't depend on fs shader
Qiang Yu
1
-2
/
+1
2018-01-09
lima: submit re-add every bo involved for each frame
Qiang Yu
6
-67
/
+17
2018-01-09
lima: use dedicated bo for each shader
Qiang Yu
4
-54
/
+66
2018-01-08
lima/gpir: assume max/min acc op comsume 2 slots
Qiang Yu
5
-90
/
+127
2018-01-08
lima/gpir: spill move also need to check acc same op
Qiang Yu
1
-5
/
+16
2018-01-06
lima: Add glColorMask support.
PaweÅ Chmiel
1
-1
/
+3
2018-01-05
nir: lower_viewport_transform store 1/w for gl_Position.w
Qiang Yu
1
-18
/
+18
2018-01-05
lima/gpir: fix two acc slot have different op
Qiang Yu
3
-0
/
+34
2018-01-04
lima: Enable back calculation of alpha_blend.
Paweł Chmiel
1
-15
/
+32
2018-01-02
lima: fix render target need aligned to 16
Qiang Yu
2
-7
/
+20
2017-12-31
lima: Handle zero scissor.
Paweł Chmiel
1
-1
/
+22
2017-12-31
lima: Create plb command for non zero scissor.
Paweł Chmiel
1
-0
/
+10
2017-12-30
lima/ppir: fix codegen bitcopy bug
Qiang Yu
1
-6
/
+6
2017-12-29
lima: Enable lowering ffma.
Paweł Chmiel
1
-0
/
+1
2017-12-29
lima: Use nir_opt_global_to_local and nir_lower_regs_to_ssa
Paweł Chmiel
1
-0
/
+5
2017-12-29
lima: Handle tgsi shaders by using tgsi_to_nir.
Paweł Chmiel
1
-4
/
+2
2017-12-20
lima/ppir: don't dup node for succs in the same instr
Qiang Yu
2
-2
/
+24
2017-12-20
lima/ppir: swap arg0/arg1 for scl acc/mul
Qiang Yu
1
-6
/
+6
2017-12-20
lima/ppir: fix target is scalar check for register
Qiang Yu
1
-3
/
+6
2017-12-20
lima/ppir: implement scale acc codegen
Qiang Yu
1
-1
/
+38
2017-12-19
lima/ppir: insert mul to add instr can only use src0
Qiang Yu
1
-6
/
+17
2017-12-19
lima/ppir: fix scl/vec mul codegen for pipeline reg dest
Qiang Yu
1
-10
/
+14
2017-12-18
lima: add nir_lower_io for mesa 17.3 port
Qiang Yu
1
-4
/
+32
2017-12-18
lima/ppir: implement scalar multiplication codegen
Vasily Khoruzhick
1
-1
/
+37
2017-12-18
lima: setup command stream for pp uniform
Vasily Khoruzhick
2
-6
/
+49
2017-12-18
lima/ppir: merge nodes into same instr if pipeline reg can be used
Qiang Yu
4
-164
/
+359
2017-12-18
lima: fix 'control reach non-void func end' warning
Qiang Yu
1
-0
/
+2
2017-12-18
lima/ppir: create with block instead of compiler
Qiang Yu
5
-55
/
+54
2017-12-18
lima/ppir: seperate node to instr from scheduler
Qiang Yu
5
-178
/
+209
2017-12-18
lima/ppir: use list to replace set for node/instr
Qiang Yu
6
-162
/
+115
2017-12-18
lima: add lima_query support stub.
Paweł Chmiel
4
-0
/
+104
2017-12-18
lima: add support for Mali450
Heiko Stuebner
4
-1
/
+13
2017-12-18
lima/gpir: remove code for complex2/impl follow complex1
Qiang Yu
2
-35
/
+3
2017-12-18
lima/gpir: optmize vreg select use round robin method
Qiang Yu
1
-3
/
+13
2017-12-18
lima/gpir: fix schedule vreg dep miss add
Qiang Yu
2
-2
/
+8
2017-12-18
lima/gpir: fix complex1 node slot calc when schedule
Qiang Yu
1
-2
/
+8
2017-12-18
lima: fix kmscube second frame skip the first draw attribute update
Qiang Yu
1
-5
/
+11
2017-12-17
lima: more command stream dump
Qiang Yu
1
-27
/
+51
2017-12-17
lima: fix clear not work
Qiang Yu
2
-14
/
+14
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