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Diffstat (limited to 'shared/radeon_drv.h')
-rw-r--r--shared/radeon_drv.h17
1 files changed, 8 insertions, 9 deletions
diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h
index 882c77fd..502ba89b 100644
--- a/shared/radeon_drv.h
+++ b/shared/radeon_drv.h
@@ -194,6 +194,7 @@ extern int radeon_emit_and_wait_irq(drm_device_t *dev);
extern int radeon_wait_irq(drm_device_t *dev, int swi_nr);
extern int radeon_emit_irq(drm_device_t *dev);
+extern void radeon_do_release(drm_device_t *dev);
/* Flags for stats.boxes
*/
@@ -821,13 +822,6 @@ do { \
* Ring control
*/
-#if defined(__powerpc__)
-#define radeon_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define radeon_flush_write_combine() DRM_WRITEMEMORYBARRIER( dev_priv->ring_rtpr )
-#endif
-
-
#define RADEON_VERBOSE 0
#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
@@ -861,8 +855,13 @@ do { \
dev_priv->ring.tail = write; \
} while (0)
-#define COMMIT_RING() do { \
- RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+#define COMMIT_RING() do { \
+ /* Flush writes to ring */ \
+ DRM_READMEMORYBARRIER(dev_priv->mmio); \
+ GET_RING_HEAD( &dev_priv->ring ); \
+ RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
+ /* read from PCI bus to ensure correct posting */ \
+ RADEON_READ( RADEON_CP_RB_RPTR ); \
} while (0)
#define OUT_RING( x ) do { \