diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/Makefile | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_dp.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_dp_auxch.c | 193 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 4 |
5 files changed, 205 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 4f277d6de594..2dd7c846305d 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -81,7 +81,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \ ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o \ - radeon_sync.o radeon_audio.o radeon_dp_mst.o + radeon_sync.o radeon_audio.o radeon_dp_mst.o radeon_dp_auxch.o radeon-$(CONFIG_MMU_NOTIFIER) += radeon_mn.o diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 071b4f4b414d..f1bc6eeead32 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -223,7 +223,10 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector) radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; - radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer; + if (radeon_auxch) + radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; + else + radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer; ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); if (!ret) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 65491bb0de14..5658b6d2b70f 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -112,6 +112,7 @@ extern int radeon_use_pflipirq; extern int radeon_bapm; extern int radeon_backlight; extern int radeon_mst; +extern int radeon_auxch; /* * Copy from radeon_drv.h so we don't have to include both and have conflicting @@ -3114,6 +3115,8 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p, uint32_t *vline_start_end, uint32_t *vline_status); +ssize_t +radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg); #include "radeon_object.h" #endif diff --git a/drivers/gpu/drm/radeon/radeon_dp_auxch.c b/drivers/gpu/drm/radeon/radeon_dp_auxch.c new file mode 100644 index 000000000000..cfaaa2258b68 --- /dev/null +++ b/drivers/gpu/drm/radeon/radeon_dp_auxch.c @@ -0,0 +1,193 @@ +#include <drm/drmP.h> +#include <drm/radeon_drm.h> +#include "radeon.h" + +#define DP_AUX_CONTROL 0x6200 + +#define DP_AUX_CONTROL_AUX_EN (1 << 0) +#define DP_AUX_CONTROL_AUX_LS_READ_EN (1 << 8) +#define DP_AUX_CONTROL_AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) +#define DP_AUX_CONTROL_AUX_HPD_DISCON(x) (((x) & 0x1) << 16) +#define DP_AUX_CONTROL_AUX_DET_EN (1 << 18) +#define DP_AUX_CONTROL_AUX_HPD_SEL(x) (((x) & 0x7) << 20) +#define DP_AUX_CONTROL_AUX_IMPCAL_REQ_EN(x) (((x) & 0x1) << 24) +#define DP_AUX_CONTROL_AUX_TEST_MODE(x) (((x) & 0x1) << 28) +#define DP_AUX_CONTROL_AUX_DEGLITCH_EN(x) (((x) & 0x1) << 28) + +#define DP_AUX_SW_CONTROL 0x6204 + +#define DP_AUX_SW_GO (1 << 0) +#define DP_AUX_LS_READ_TRIG(x) (((x) & 0x1) << 2) +#define DP_AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) +#define DP_AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) + +#define DP_AUX_SW_INTERRUPT_CONTROL 0x620c +#define DP_AUX_SW_DONE_INT (1 << 0) +#define DP_AUX_SW_DONE_ACK (1 << 1) +#define DP_AUX_SW_DONE_MASK (1 << 2) +#define DP_AUX_SW_LS_DONE_INT (1 << 4) +#define DP_AUX_SW_LS_DONE_MASK (1 << 6) + +#define DP_AUX_SW_STATUS 0x6210 +#define DP_AUX_SW_DONE (1 << 0) +#define DP_AUX_SW_REQ (1 << 1) +#define DP_AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) +#define DP_AUX_SW_RX_TIMEOUT (1 << 7) +#define DP_AUX_SW_RX_OVERFLOW (1 << 8) +#define DP_AUX_SW_RX_HPD_DISCON (1 << 9) + +#define DP_AUX_SW_DATA 0x6218 +#define DP_AUX_SW_DATA_RW (1 << 0) +#define DP_AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) +#define DP_AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) +#define DP_AUX_SW_AUTOINCREMENT_DISABLE (1 << 31) + +static uint32_t dce5_dp_base[6] = { 0x6200, + 0x6250, + 0x62a0, + 0x6300, + 0x6350, + 0x63a0 }; + +/* native implementation of AUXCH for DCE5 */ +#define DPREG(x) (((x) - 0x6200) + offset) + +#define DBG_WREG32(reg, val) do { \ + DRM_DEBUG_KMS("writing %08x: %08x\n", reg, val); \ + WREG32(reg, val); \ + } while(0) +ssize_t +radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) +{ + struct radeon_i2c_chan *chan = + container_of(aux, struct radeon_i2c_chan, aux); + struct drm_device *dev = chan->dev; + struct radeon_device *rdev = dev->dev_private; + int ret = 0, i; + uint32_t tmp, ack = 0; + uint32_t offset = dce5_dp_base[chan->rec.i2c_id & 0xf]; + u8 byte; + u8 *buf; + int retry_count = 0; + int nbytes; + int wbytes = 3; + int msize; + bool is_write = false; + if (WARN_ON(msg->size > 16)) + return -E2BIG; + + DRM_DEBUG_KMS("%d/%d: native transfer request addr:%x size:%ld req:%x\n", chan->rec.i2c_id & 0xf, chan->rec.hpd, msg->address, msg->size, msg->request); + mutex_lock(&chan->mutex); + + DBG_WREG32(0x6430, 0xf010000); + tmp = RREG32(DPREG(DP_AUX_CONTROL)); + + tmp &= DP_AUX_CONTROL_AUX_HPD_SEL(0x7); + tmp |= DP_AUX_CONTROL_AUX_HPD_SEL(chan->rec.hpd); + + tmp |= DP_AUX_CONTROL_AUX_EN | DP_AUX_CONTROL_AUX_LS_READ_EN; + + DBG_WREG32(DPREG(DP_AUX_CONTROL), tmp); + + switch (msg->request & ~DP_AUX_I2C_MOT) { + case DP_AUX_NATIVE_WRITE: + case DP_AUX_I2C_WRITE: + is_write = true; + break; + default: + break; + } + + msize = msg->size ? msg->size - 1 : 0; + wbytes += is_write ? msg->size : 1; + + DBG_WREG32(DPREG(DP_AUX_SW_CONTROL), + DP_AUX_SW_WR_BYTES(wbytes)); + DBG_WREG32(DPREG(DP_AUX_SW_CONTROL), + DP_AUX_SW_WR_BYTES(wbytes)); + /* write the data headers into the registers */ + byte = (msg->request << 4); + DBG_WREG32(DPREG(DP_AUX_SW_DATA), + DP_AUX_SW_DATA_MASK(byte) | DP_AUX_SW_AUTOINCREMENT_DISABLE); + byte = (msg->address >> 8) & 0xff; + DBG_WREG32(DPREG(DP_AUX_SW_DATA), + DP_AUX_SW_DATA_MASK(byte)); + byte = msg->address & 0xff; + DBG_WREG32(DPREG(DP_AUX_SW_DATA), + DP_AUX_SW_DATA_MASK(byte)); + byte = msize; + DBG_WREG32(DPREG(DP_AUX_SW_DATA), + DP_AUX_SW_DATA_MASK(byte)); + + if (is_write) { + buf = msg->buffer; + for (i = 0; i < msg->size; i++) { + DBG_WREG32(DPREG(DP_AUX_SW_DATA), + DP_AUX_SW_DATA_MASK(buf[i])); + } + } + + DBG_WREG32(DPREG(DP_AUX_SW_INTERRUPT_CONTROL), DP_AUX_SW_DONE_ACK); + + DBG_WREG32(DPREG(DP_AUX_SW_CONTROL), + DP_AUX_SW_WR_BYTES(wbytes) | DP_AUX_SW_GO); + + do { + tmp = RREG32(DPREG(DP_AUX_SW_STATUS)); + if (tmp & DP_AUX_SW_DONE) { + DRM_DEBUG_KMS("got aux done %08x\n", tmp); + break; + } + usleep_range(100, 200); + } while (retry_count++ < 1000); + + if (retry_count >= 1000) { + DRM_ERROR("retried a lot and failed %x: %d\n", tmp, (tmp >> 24) & 0x1f); + ret = -EIO; + goto done; + } + + if (tmp & (0x1 << 7)) { + DRM_DEBUG_KMS("dp_aux_ch timed out\n"); + ret = -ETIMEDOUT; + goto done; + } + if (tmp & ((0xf << 8))) { + DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); + ret = -EIO; + goto done; + } + + nbytes = (tmp >> 24) & 0x1f; + if (nbytes) { + buf = msg->buffer; + + DRM_DEBUG_KMS("nbytes reported %d\n", nbytes); + + WREG32(DPREG(DP_AUX_SW_DATA), + DP_AUX_SW_DATA_RW | DP_AUX_SW_AUTOINCREMENT_DISABLE); + tmp = RREG32(DPREG(DP_AUX_SW_DATA)); + ack = (tmp >> 8) & 0xff; + DRM_DEBUG_KMS("status byte: %08x %x\n", tmp, ack); + for (i = 0; i < nbytes - 1; i++) { + tmp = RREG32(DPREG(DP_AUX_SW_DATA)); + DRM_DEBUG_KMS("byte %d: %08x\n", i + 1, tmp); + if (buf) + buf[i] = (tmp >> 8) & 0xff; + } + if (buf) + ret = nbytes - 1; + } + + DBG_WREG32(DPREG(DP_AUX_SW_INTERRUPT_CONTROL), DP_AUX_SW_DONE_ACK); + + if (is_write) + ret = msg->size; +done: + mutex_unlock(&chan->mutex); + + + if (ret >= 0) + msg->reply = ack >> 4; + return ret; +} diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 93a986cf5e5e..65ae74718b6f 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -191,6 +191,7 @@ int radeon_use_pflipirq = 2; int radeon_bapm = -1; int radeon_backlight = -1; int radeon_mst = 0; +int radeon_auxch = 0; MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); module_param_named(no_wb, radeon_no_wb, int, 0444); @@ -279,6 +280,9 @@ module_param_named(backlight, radeon_backlight, int, 0444); MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)"); module_param_named(mst, radeon_mst, int, 0444); +MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable)"); +module_param_named(auxch, radeon_auxch, int, 0444); + static struct pci_device_id pciidlist[] = { radeon_PCI_IDS }; |