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-rw-r--r--src/regsmi.h4
-rw-r--r--src/smi.h4
-rw-r--r--src/smi_501.c6
-rw-r--r--src/smi_501.h26
-rw-r--r--src/smi_driver.c42
5 files changed, 53 insertions, 29 deletions
diff --git a/src/regsmi.h b/src/regsmi.h
index b77b6ff..209622c 100644
--- a/src/regsmi.h
+++ b/src/regsmi.h
@@ -189,12 +189,12 @@ VGAOUT8(SMIPtr pSmi, int port, CARD8 data)
/* Wait until "v" queue entries are free */
/**** FIXME
**** This is completely ilogical. Argument "v" is ignored, and
- **** pSmi->NoPCIRetry defaults to true (but on smi sources this
+ **** pSmi->PCIRetry defaults to false (but on smi sources this
**** macro is a noop and will get stuck on engine reset timeouts if enabled...)
***/
#define WaitQueue(v) \
do { \
- if (!IS_MSOC(pSmi) && pSmi->NoPCIRetry) { \
+ if (!IS_MSOC(pSmi) && !pSmi->PCIRetry) { \
int loop = MAXLOOP; mem_barrier(); \
while (!FIFO_EMPTY()) \
if (loop-- == 0) break; \
diff --git a/src/smi.h b/src/smi.h
index 4b3c553..97a1f55 100644
--- a/src/smi.h
+++ b/src/smi.h
@@ -165,9 +165,9 @@ typedef struct
int GEResetCnt; /* Limit the number of errors
printed using a counter */
- Bool pci_burst; /* Enable PCI burst mode for
+ Bool PCIBurst; /* Enable PCI burst mode for
reads? */
- Bool NoPCIRetry; /* Disable PCI retries */
+ Bool PCIRetry; /* Enable PCI retries */
Bool fifo_conservative; /* Adjust fifo for
acceleration? */
Bool fifo_moderate; /* Adjust fifo for
diff --git a/src/smi_501.c b/src/smi_501.c
index 190ada0..725ab7a 100644
--- a/src/smi_501.c
+++ b/src/smi_501.c
@@ -485,6 +485,12 @@ SMI501_ModeInit(ScrnInfoPtr pScrn, DisplayModePtr xf86mode)
WRITE_SCR(pSmi, POWER_CTL, mode->power_ctl.value);
+ if (pSmi->PCIBurst) {
+ field(mode->system_ctl, burst) = field(mode->system_ctl, burst_read) = 1;
+ field(mode->system_ctl, retry) = pSmi->PCIRetry != FALSE;
+ WRITE_SCR(pSmi, SYSTEM_CTL, mode->system_ctl.value);
+ }
+
/* FIXME update pallete here if running at 8 bpp */
SMI_AdjustFrame(pScrn->scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
diff --git a/src/smi_501.h b/src/smi_501.h
index f49630a..9ade949 100644
--- a/src/smi_501.h
+++ b/src/smi_501.h
@@ -52,15 +52,31 @@ typedef struct _MSOCRegRec {
* Read/Write MMIO_base + 0x000000
* Power-on Default 0b0000.0000.XX0X.X0XX.0000.0000.0000.0000
*
+ * 7:7 PCI Retry
+ * 0: Enable
+ * 1: Disable
+ * 15:15 PCI Burst Read Enable.
+ * The BE bit must be enabled as well for this bit to take effect.
+ * (BE bit is bit 29, bit 15 is BrE)
+ * 0: Disable.
+ * 1: Enable.
+ * 29:29 PCI Burst Enable.
+ * 0: Disable.
+ * 1: Enable.
* 30:31 Vertical Sync Horizontal Sync
- * 00 Pulsing Pulsing
- * 01 Pulsing Not pulsing
- * 10 Not pulsing Pulsing
- * 11 Not pulsing Not pulsing
+ * 00 Pulsing Pulsing
+ * 01 Pulsing Not pulsing
+ * 10 Not pulsing Pulsing
+ * 11 Not pulsing Not pulsing
*/
union {
struct {
- int32_t u0 : bitfield( 0, 29);
+ int32_t u0 : bitfield( 0, 6);
+ int32_t retry : bitfield( 7, 7);
+ int32_t u1 : bitfield( 8, 14);
+ int32_t burst_read : bitfield(15, 15);
+ int32_t u2 : bitfield(16, 28);
+ int32_t burst : bitfield(29, 29);
int32_t dpmsh : bitfield(30, 30);
int32_t dpmsv : bitfield(31, 31);
} detail;
diff --git a/src/smi_driver.c b/src/smi_driver.c
index 0cf91cb..bccecb4 100644
--- a/src/smi_driver.c
+++ b/src/smi_driver.c
@@ -182,11 +182,11 @@ typedef enum
static const OptionInfoRec SMIOptions[] =
{
- { OPTION_PCI_BURST, "pci_burst", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_PCI_BURST, "pci_burst", OPTV_BOOLEAN, {0}, TRUE },
{ OPTION_FIFO_CONSERV, "fifo_conservative", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_FIFO_MODERATE, "fifo_moderate", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_FIFO_AGGRESSIVE, "fifo_aggressive", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_PCI_RETRY, "pci_retry", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_FIFO_AGGRESSIVE, "fifo_aggressive", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_PCI_RETRY, "pci_retry", OPTV_BOOLEAN, {0}, TRUE },
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_MCLK, "set_mclk", OPTV_FREQ, {0}, FALSE },
{ OPTION_SHOWCACHE, "show_cache", OPTV_BOOLEAN, {0}, FALSE },
@@ -541,7 +541,6 @@ SMI_PreInit(ScrnInfoPtr pScrn, int flags)
int i;
ClockRangePtr clockRanges;
char *s;
- int mclk;
vgaHWPtr hwp;
int vgaCRIndex, vgaIOBase;
vbeInfoPtr pVbe = NULL;
@@ -687,24 +686,27 @@ SMI_PreInit(ScrnInfoPtr pScrn, int flags)
memcpy(pSmi->Options, SMIOptions, sizeof(SMIOptions));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pSmi->Options);
- if (xf86ReturnOptValBool(pSmi->Options, OPTION_PCI_BURST, FALSE)) {
- pSmi->pci_burst = TRUE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: pci_burst - PCI burst "
- "read enabled\n");
- } else {
- pSmi->pci_burst = FALSE;
- }
+ /* Enable pci burst by default */
+ from = X_PROBED;
+ pSmi->PCIBurst = TRUE;
+ if (xf86GetOptValBool(pSmi->Options, OPTION_PCI_BURST, &pSmi->PCIBurst))
+ from = X_CONFIG;
+ xf86DrvMsg(pScrn->scrnIndex, from, "PCI Burst %sabled\n",
+ pSmi->PCIBurst ? "en" : "dis");
- pSmi->NoPCIRetry = TRUE;
- if (xf86ReturnOptValBool(pSmi->Options, OPTION_PCI_RETRY, FALSE)) {
- if (xf86ReturnOptValBool(pSmi->Options, OPTION_PCI_BURST, FALSE)) {
- pSmi->NoPCIRetry = FALSE;
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Option: pci_retry\n");
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "\"pci_retry\" option "
- "requires \"pci_burst\".\n");
+ /* Pci retry enabled by default if pci burst also enabled */
+ from = X_PROBED;
+ pSmi->PCIRetry = pSmi->PCIBurst ? TRUE : FALSE;
+ if (xf86GetOptValBool(pSmi->Options, OPTION_PCI_RETRY, &pSmi->PCIRetry)) {
+ from = X_CONFIG;
+ if (pSmi->PCIRetry && !pSmi->PCIBurst) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "\"pci_retry\" option requires \"pci_burst\".\n");
+ pSmi->PCIRetry = FALSE;
}
}
+ xf86DrvMsg(pScrn->scrnIndex, from, "PCI Retry %sabled\n",
+ pSmi->PCIRetry ? "en" : "dis");
if (xf86IsOptionSet(pSmi->Options, OPTION_FIFO_CONSERV)) {
pSmi->fifo_conservative = TRUE;
@@ -2679,7 +2681,7 @@ SMI_ModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
outb(pSmi->PIOBase + VGA_SEQ_INDEX, 0x17);
tmp = inb(pSmi->PIOBase + VGA_SEQ_DATA);
- if (pSmi->pci_burst) {
+ if (pSmi->PCIBurst) {
new->SR17 = tmp | 0x20;
} else {
new->SR17 = tmp & ~0x20;
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-22 04:26:48 +0000