diff options
| author | Paulo Cesar Pereira de Andrade <pcpa@mandriva.com.br> | 2008-09-18 18:10:54 -0300 |
|---|---|---|
| committer | Paulo Cesar Pereira de Andrade <pcpa@mandriva.com.br> | 2008-09-18 18:10:54 -0300 |
| commit | 95e312b712a1e4a476ef31c5302faf77c22915a9 (patch) | |
| tree | 1cdca7d0b1048f165a2d38bee600b51c3449af69 | |
| parent | cf5132907e4709c872089fe2d79837b2de4e45b7 (diff) | |
Complete rewrite of smi_501.c and smi_501.h.
The previous version was dependant on kernel framebuffer, as it was
just failing a test if not having a modeline defined, and in the test
case, it is running at 1024x600.
Now it properly programs the video hardware, and the procedure is
expected to be very well documented.
| -rw-r--r-- | src/smi_501.c | 1267 | ||||
| -rw-r--r-- | src/smi_501.h | 1898 |
2 files changed, 1112 insertions, 2053 deletions
diff --git a/src/smi_501.c b/src/smi_501.c index 0d7c7fa..190ada0 100644 --- a/src/smi_501.c +++ b/src/smi_501.c @@ -1,8 +1,7 @@ -/* Header: //Mercury/Projects/archives/XFree86/4.0/smi_driver.c-arc 1.42 03 Jan 2001 13:52:16 Frido $ */ - /* Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. Copyright (C) 2000 Silicon Motion, Inc. All Rights Reserved. +Copyright (C) 2008 Mandriva Linux. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in @@ -26,7 +25,6 @@ Silicon Motion shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from The XFree86 Project or Silicon Motion. */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/siliconmotion/smi_driver.c,v 1.30 2003/04/23 21:51:44 tsi Exp $ */ #ifdef HAVE_CONFIG_H #include "config.h" @@ -47,906 +45,543 @@ authorization from The XFree86 Project or Silicon Motion. #define DPMS_SERVER #include <X11/extensions/dpms.h> +/* Want to see register dumps for now */ +#undef VERBLEV +#define VERBLEV 1 -/* - * Forward definitions for the functions that make up the driver. - */ -static int roundDiv(int num, int denom); -static int findClock(int requested_clock, clock_select_t *clock, - display_t display); -static mode_table_t *findMode(mode_table_t *mode_table, int width, int height, - int refresh_rate); -static void adjustMode(mode_table_t *vesaMode, mode_table_t *mode, - display_t display); -static void setModeRegisters(reg_table_t *register_table, mode_table_t *mode, - display_t display, int bpp, int fbPitch); -static void programMode(SMIPtr pSmi, reg_table_t *register_table); -static void SetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, - unsigned int fMode, unsigned int nHertz, display_t display, - int fbPitch, int bpp); -static void panelSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, - unsigned int fMode, unsigned int nHertz, int fbPitch, - int bpp); -static void crtSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, - unsigned int fMode, unsigned int nHertz, int fbPitch, - int bpp); -static void setPower(SMIPtr pSmi, unsigned int nGates, unsigned int Clock); -static void panelWaitVSync(SMIPtr pSmi, int vsync_count); -static void panelPowerSequence(SMIPtr pSmi, panel_state_t on_off, - int vsync_delay); -static void panelUseCRT(SMIPtr pSmi, BOOL bEnable); +static char *format_integer_base2(int32_t word); +static void SMI501_PrintRegs(ScrnInfoPtr pScrn); +static void SMI501_SetClock(SMIPtr pSmi, int32_t port, + int32_t clock, int32_t value); +static void SMI501_WaitVSync(SMIPtr pSmi, int vsync_count); -/* - * Add comment here about this module. - */ - -/* Mode table. */ -mode_table_t mode_table[] = { - /*---------------------------------------------------------------------------------------- - * H. H. H. H. H. V. V. V. V. V. Pixel H. V. - * tot. disp. sync sync sync tot. disp. sync sync sinc clock freq. freq. - * end start wdth polarity end start hght polarity - *---------------------------------------------------------------------------------------*/ - - /* 640 x 480 */ - { 800, 640, 656, 96, NEGATIVE, 525, 480, 490, 2, NEGATIVE, 25175000, 31469, 60 }, - { 832, 640, 664, 40, NEGATIVE, 520, 480, 489, 3, NEGATIVE, 31500000, 37861, 72 }, - { 840, 640, 656, 64, NEGATIVE, 500, 480, 481, 3, NEGATIVE, 31500000, 37500, 75 }, - { 832, 640, 696, 56, NEGATIVE, 509, 480, 481, 3, NEGATIVE, 36000000, 43269, 85 }, - - /* 800 x 600 */ - { 1024, 800, 824, 72, POSITIVE, 625, 600, 601, 2, POSITIVE, 36000000, 35156, 56 }, - { 1056, 800, 840, 128, POSITIVE, 628, 600, 601, 4, POSITIVE, 40000000, 37879, 60 }, - { 1040, 800, 856, 120, POSITIVE, 666, 600, 637, 6, POSITIVE, 50000000, 48077, 72 }, - { 1056, 800, 816, 80, POSITIVE, 625, 600, 601, 3, POSITIVE, 49500000, 46875, 75 }, - { 1048, 800, 832, 64, POSITIVE, 631, 600, 601, 3, POSITIVE, 56250000, 53674, 85 }, - - /* 1024 x 768*/ - { 1344, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 65000000, 48363, 60 }, - { 1328, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 75000000, 56476, 70 }, - { 1312, 1024, 1040, 96, POSITIVE, 800, 768, 769, 3, POSITIVE, 78750000, 60023, 75 }, - { 1376, 1024, 1072, 96, POSITIVE, 808, 768, 769, 3, POSITIVE, 94500000, 68677, 85 }, - - /* End of table. */ - { 0, 0, 0, 0, NEGATIVE, 0, 0, 0, 0, NEGATIVE, 0, 0, 0 }, -}; - - -/* Set DPMS state. */ -void -SMI501_SetDPMS(SMIPtr pSmi, DPMS_t state) +Bool +SMI501_EnterVT(int scrnIndex, int flags) { - unsigned int value; + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + SMIPtr pSmi = SMIPTR(pScrn); + Bool result; - value = SMI501_Read32(pSmi, SYSTEM_CTRL); - switch (state) { - case DPMS_ON: - value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VPHP); - break; + /* Enable MMIO and map memory */ + SMI_MapMem(pScrn); - case DPMS_STANDBY: - value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VPHN); - break; + pSmi->Save(pScrn); - case DPMS_SUSPEND: - value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VNHP); - break; + /* FBBase may have changed after remapping the memory */ + pScrn->pixmapPrivate.ptr = pSmi->FBBase; + if(pSmi->useEXA) + pSmi->EXADriverPtr->memoryBase = pSmi->FBBase; - case DPMS_OFF: - value = FIELD_SET(value, SYSTEM_CTRL, DPMS, VNHN); - break; + /* #670 */ + if (pSmi->shadowFB) { + pSmi->FBOffset = pSmi->savedFBOffset; + pSmi->FBReserved = pSmi->savedFBReserved; } - SMI501_Write32(pSmi, SYSTEM_CTRL, value); -} - -Bool -SMI501_SetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) -{ - SMIPtr pSmi = SMIPTR(pScrn); + result = pSmi->ModeInit(pScrn, pScrn->currentMode); - ENTER_PROC("SMI501_SetMode"); + if (result && pSmi->shadowFB) { + BoxRec box; - /* FIXME */ - mode->VRefresh = 60; - - if (pSmi->IsSecondary) - crtSetMode(pSmi, mode->HDisplay, mode->VDisplay, 0, mode->VRefresh, pSmi->Stride, pScrn->depth); - else - panelSetMode(pSmi, mode->HDisplay, mode->VDisplay, 0, mode->VRefresh, pSmi->Stride, pScrn->depth); + if (pSmi->pSaveBuffer) { + memcpy(pSmi->FBBase, pSmi->pSaveBuffer, pSmi->saveBufferSize); + xfree(pSmi->pSaveBuffer); + pSmi->pSaveBuffer = NULL; + } - panelUseCRT(pSmi, TRUE); /* Enable both outputs simultaneously */ - LEAVE_PROC("SMI501_SetMode"); + box.x1 = 0; + box.y1 = 0; + box.x2 = pSmi->width; + box.y2 = pSmi->height; + SMI_RefreshArea(pScrn, 1, &box); + } - return TRUE; + /* Reset the grapics engine */ + if (!pSmi->NoAccel) + SMI_EngineReset(pScrn); + return (result); } -/********************************************************************** - * SMI501_Read32 - * Read the value of the 32-bit register specified by nOffset - **********************************************************************/ -unsigned int -SMI501_Read32(SMIPtr pSmi, unsigned int nOffset) +void +SMI501_LeaveVT(int scrnIndex, int flags) { - unsigned int result; + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + SMIPtr pSmi = SMIPTR(pScrn); - result = READ_SCR(pSmi, nOffset); + if (pSmi->shadowFB) { + pSmi->pSaveBuffer = xnfalloc(pSmi->saveBufferSize); + if (pSmi->pSaveBuffer) + memcpy(pSmi->pSaveBuffer, pSmi->FBBase, pSmi->saveBufferSize); - return (result); + pSmi->savedFBOffset = pSmi->FBOffset; + pSmi->savedFBReserved = pSmi->FBReserved; + } + + memset(pSmi->FBBase, 0, 256 * 1024); + SMI_UnmapMem(pScrn); } -/********************************************************************** - * SMI501_Write32 - * Write the 32-bit value, nData, to the 32-bit register specified by - * nOffset - **********************************************************************/ void -SMI501_Write32(SMIPtr pSmi, unsigned int nOffset, unsigned int nData) +SMI501_Save(ScrnInfoPtr pScrn) { - WRITE_SCR(pSmi, nOffset, nData); -} + SMIPtr pSmi = SMIPTR(pScrn); + MSOCRegPtr save = pSmi->save; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, VERBLEV, + "Register dump (Before Save)\n"); + SMI501_PrintRegs(pScrn); + + /* Used mainly for DPMS info */ + save->system_ctl.value = READ_SCR(pSmi, SYSTEM_CTL); + + /* Used basically to enable dac */ + save->misc_ctl.value = READ_SCR(pSmi, MISC_CTL); + /* Read it first to know if current power mode */ + save->power_ctl.value = READ_SCR(pSmi, POWER_CTL); + + switch (field(save->power_ctl, mode)) { + case 0: + save->current_gate = POWER0_GATE; + save->current_clock = POWER0_CLOCK; + break; + case 1: + save->current_gate = POWER1_GATE; + save->current_clock = POWER1_CLOCK; + break; + default: + /* FIXME + * Should be in sleep mode + * TODO + * select mode0 by default + */ + save->current_gate = POWER0_GATE; + save->current_clock = POWER0_CLOCK; + break; + } + + save->gate.value = READ_SCR(pSmi, save->current_gate); + save->clock.value = READ_SCR(pSmi, save->current_clock); + + /* FIXME Never changed */ + save->power_ctl.value = READ_SCR(pSmi, TIMING_CONTROL); + + save->sleep_gate.value = READ_SCR(pSmi, SLEEP_GATE); + + save->panel_display_ctl.value = READ_SCR(pSmi, PANEL_DISPLAY_CTL); + save->panel_fb_address.value = READ_SCR(pSmi, PANEL_FB_ADDRESS); + save->panel_fb_width.value = READ_SCR(pSmi, PANEL_FB_WIDTH); + save->panel_wwidth.value = READ_SCR(pSmi, PANEL_WWIDTH); + save->panel_wheight.value = READ_SCR(pSmi, PANEL_WHEIGHT); + save->panel_plane_tl.value = READ_SCR(pSmi, PANEL_PLANE_TL); + save->panel_plane_br.value = READ_SCR(pSmi, PANEL_PLANE_BR); + save->panel_htotal.value = READ_SCR(pSmi, PANEL_HTOTAL); + save->panel_hsync.value = READ_SCR(pSmi, PANEL_HSYNC); + save->panel_vtotal.value = READ_SCR(pSmi, PANEL_VTOTAL); + save->panel_vsync.value = READ_SCR(pSmi, PANEL_VSYNC); + + save->crt_display_ctl.value = READ_SCR(pSmi, CRT_DISPLAY_CTL); + save->crt_fb_address.value = READ_SCR(pSmi, CRT_FB_ADDRESS); + save->crt_fb_width.value = READ_SCR(pSmi, CRT_FB_WIDTH); + save->crt_htotal.value = READ_SCR(pSmi, CRT_HTOTAL); + save->crt_hsync.value = READ_SCR(pSmi, CRT_HSYNC); + save->crt_vtotal.value = READ_SCR(pSmi, CRT_VTOTAL); + save->crt_vsync.value = READ_SCR(pSmi, CRT_VSYNC); +} -/* Perform a rounded division. */ -static int -roundDiv(int num, int denom) +void +SMI501_DisplayPowerManagementSet(ScrnInfoPtr pScrn, + int PowerManagementMode, int flags) { - /* n / d + 1 / 2 = (2n + d) / 2d */ - return (2 * num + denom) / (2 * denom); + SMIPtr pSmi = SMIPTR(pScrn); + MSOCRegPtr mode = pSmi->mode; + + if (pSmi->CurrentDPMS != PowerManagementMode) { + mode->system_ctl.value = READ_SCR(pSmi, SYSTEM_CTL); + switch (PowerManagementMode) { + case DPMSModeOn: + field(mode->system_ctl, dpmsh) = 1; + field(mode->system_ctl, dpmsv) = 1; + break; + case DPMSModeStandby: + field(mode->system_ctl, dpmsh) = 0; + field(mode->system_ctl, dpmsv) = 1; + break; + case DPMSModeSuspend: + field(mode->system_ctl, dpmsh) = 1; + field(mode->system_ctl, dpmsv) = 0; + break; + case DPMSModeOff: + field(mode->system_ctl, dpmsh) = 0; + field(mode->system_ctl, dpmsv) = 0; + break; + } + WRITE_SCR(pSmi, SYSTEM_CTL, mode->system_ctl.value); + pSmi->CurrentDPMS = PowerManagementMode; + } } -/* Finds clock closest to the requested. */ -static int -findClock(int requested_clock, clock_select_t *clock, display_t display) +Bool +SMI501_ModeInit(ScrnInfoPtr pScrn, DisplayModePtr xf86mode) { - int mclk; - int divider, shift; - int best_diff = 999999999; - - /* Try 288MHz and 336MHz clocks. */ - for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { - /* For CRT, try dividers 1 and 3, for panel, try divider 5 as well. */ - for (divider = 1; divider <= (display == PANEL ? 5 : 3); divider += 2) { - /* Try all 8 shift values. */ - for (shift = 0; shift < 8; shift++) { - /* Calculate difference with requested clock. */ - int diff = roundDiv(mclk, (divider << shift)) - requested_clock; + MSOCRegPtr save; + MSOCRegPtr mode; + SMIPtr pSmi = SMIPTR(pScrn); + double mclk; + int32_t clock; + int diff, best, divider, shift, x2_divider, x2_shift; + + save = pSmi->save; + mode = pSmi->mode; + + pSmi->Bpp = pScrn->bitsPerPixel / 8; + if (pSmi->rotate) { + pSmi->width = pScrn->virtualY; + pSmi->height = pScrn->virtualX; + pSmi->Stride = (pSmi->height * pSmi->Bpp + 15) & ~15; + } + else { + pSmi->width = pScrn->virtualX; + pSmi->height = pScrn->virtualY; + pSmi->Stride = (pSmi->width * pSmi->Bpp + 15) & ~15; + } + + /* Start with a fresh copy of registers before any mode change */ + memcpy(mode, save, sizeof(MSOCRegRec)); + + /* Enable DAC -- 0: enable - 1: disable */ + field(mode->misc_ctl, dac) = 0; + + /* Enable 2D engine */ + field(mode->gate, engine) = 1; + /* Color space conversion */ + field(mode->gate, csc) = 1; + /* ZV port */ + field(mode->gate, zv) = 1; + /* Gpio, Pwm, and I2c */ + field(mode->gate, gpio) = 1; + + /* Update gate first */ + WRITE_SCR(pSmi, mode->current_gate, mode->gate.value); + + /* FIXME fixed at power mode 0 as in the smi sources */ + field(mode->power_ctl, status) = 0; + field(mode->power_ctl, mode) = 0; + + /* FIXME fixed at 336/3/0 as in the smi sources */ + field(mode->clock, m_select) = 1; + clock = mode->clock.value; + field(mode->clock, m_divider) = 1; + field(mode->clock, m_shift) = 0; + SMI501_SetClock(pSmi, mode->current_clock, clock, mode->clock.value); + + switch (pSmi->MCLK) { + case 168000: /* 336/1/1 */ + field(mode->clock, m2_select) = 1; + clock = mode->clock.value; + field(mode->clock, m2_divider) = 0; + field(mode->clock, m2_shift) = 1; + break; + case 96000: /* 288/3/0 */ + field(mode->clock, m2_select) = 0; + clock = mode->clock.value; + field(mode->clock, m2_divider) = 1; + field(mode->clock, m2_shift) = 0; + break; + case 144000: /* 288/1/1 */ + field(mode->clock, m2_select) = 0; + clock = mode->clock.value; + field(mode->clock, m2_divider) = 0; + field(mode->clock, m2_shift) = 1; + break; + case 112000: /* 336/3/0 */ + default: + field(mode->clock, m2_select) = 1; + clock = mode->clock.value; + field(mode->clock, m2_divider) = 1; + field(mode->clock, m2_shift) = 0; + break; + } + SMI501_SetClock(pSmi, mode->current_clock, clock, mode->clock.value); + + /* Find clock best matching mode */ + best = 0x7fffffff; + for (mclk = 288000.0; mclk <= 336000.0; mclk += 48000.0) { + for (divider = 1; divider <= (pSmi->lcd ? 5 : 3); divider += 2) { + /* Start at 1 to match division by 2 */ + for (shift = 1; shift <= 8; shift++) { + /* Shift starts at 1 to add a division by two, matching + * description of P2XCLK and V2XCLK. */ + diff = (mclk / (divider << shift)) - xf86mode->Clock; if (diff < 0) diff = -diff; + if (diff < best) { + x2_shift = shift - 1; + x2_divider = divider == 1 ? 0 : divider == 3 ? 1 : 2; - /* If the difference is less than the current, use it. */ - if (diff < best_diff) { - /* Store best difference. */ - best_diff = diff; - - /* Store clock values. */ - clock->mclk = mclk; - clock->divider = divider; - clock->shift = shift; + /* Remember best diff */ + best = diff; } } } } - /* Return best clock. */ - return clock->mclk / (clock->divider << clock->shift); -} + if (pSmi->lcd) { + field(mode->clock, p2_select) = mclk == 288000.0 ? 0 : 1; + clock = mode->clock.value; + field(mode->clock, p2_divider) = x2_divider; + field(mode->clock, p2_shift) = x2_shift; + SMI501_SetClock(pSmi, mode->current_clock, clock, mode->clock.value); + field(mode->panel_display_ctl, format) = + pScrn->bitsPerPixel == 8 ? 0 : + pScrn->bitsPerPixel == 16 ? 1 : 2; -/* Finds the requested mode in the mode table. */ -static mode_table_t * -findMode(mode_table_t *mode_table, int width, int height, int refresh_rate) -{ - /* Walk the entire mode table. */ - while (mode_table->pixel_clock != 0) { - /* If this mode matches the requested mode, return it! */ - if (mode_table->horizontal_display_end == width && - mode_table->vertical_display_end == height && - mode_table->vertical_frequency == refresh_rate) - return (mode_table); - - /* Next entry in the mode table. */ - mode_table++; - } + field(mode->panel_display_ctl, enable) = 1; + field(mode->panel_display_ctl, timing) = 1; - /* No mode found. */ - return (NULL); -} + /* FIXME if non clone dual head, and secondary, need to + * properly set panel fb address properly ... */ + field(mode->panel_fb_address, address) = 0; + field(mode->panel_fb_address, mextern) = 0; /* local memory */ + field(mode->panel_fb_address, pending) = 0; /* FIXME required? */ -/* Converts the VESA timing into Voyager timing. */ -static void -adjustMode(mode_table_t *vesaMode, mode_table_t *mode, display_t display) -{ - int blank_width, sync_start, sync_width; - clock_select_t clock; - - /* Calculate the VESA line and screen frequencies. */ - vesaMode->horizontal_frequency = roundDiv(vesaMode->pixel_clock, - vesaMode->horizontal_total); - vesaMode->vertical_frequency = roundDiv(vesaMode->horizontal_frequency, - vesaMode->vertical_total); - - /* Calculate the sync percentages of the VESA mode. */ - blank_width = vesaMode->horizontal_total - vesaMode->horizontal_display_end; - sync_start = roundDiv((vesaMode->horizontal_sync_start - - vesaMode->horizontal_display_end) * 100, blank_width); - sync_width = roundDiv(vesaMode->horizontal_sync_width * 100, blank_width); - - /* Copy VESA mode into Voyager mode. */ - *mode = *vesaMode; - - /* Find the best pixel clock. */ - mode->pixel_clock = findClock(vesaMode->pixel_clock * 2, - &clock, display) / 2; - - /* Calculate the horizontal total based on the pixel clock and VESA line - * frequency. */ - mode->horizontal_total = roundDiv(mode->pixel_clock, - vesaMode->horizontal_frequency); - - /* Calculate the sync start and width based on the VESA percentages. */ - blank_width = mode->horizontal_total - mode->horizontal_display_end; - mode->horizontal_sync_start = mode->horizontal_display_end + - roundDiv(blank_width * sync_start, 100); - mode->horizontal_sync_width = roundDiv(blank_width * sync_width, 100); - - /* Calculate the line and screen frequencies. */ - mode->horizontal_frequency = roundDiv(mode->pixel_clock, - mode->horizontal_total); - mode->vertical_frequency = roundDiv(mode->horizontal_frequency, - mode->vertical_total); -} + /* >> 4 because of the "unused bits" that should be set to 0 */ + /* FIXME this should be used for virtual size? */ + field(mode->panel_fb_width, offset) = pSmi->Stride >> 4; + field(mode->panel_fb_width, width) = pSmi->Stride >> 4; -/* Fill the register structure. */ -static void -setModeRegisters(reg_table_t *register_table, mode_table_t *mode, - display_t display, int bpp, int fbPitch) -{ - clock_select_t clock; - - memset(&clock, 0, sizeof(clock)); - - /* Calculate the clock register values. */ - findClock(mode->pixel_clock * 2, &clock, display); - - if (display == PANEL) { - /* Set clock value for panel. */ - register_table->clock = - (clock.mclk == 288000000 ? - FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_SELECT, 288) : - FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_SELECT, 336)) | - (clock.divider == 1 ? - FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 1) : - (clock.divider == 3 ? - FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 3) : - FIELD_SET(0, CURRENT_POWER_CLOCK, P2XCLK_DIVIDER, 5))) | - FIELD_VALUE(0, CURRENT_POWER_CLOCK, P2XCLK_SHIFT, clock.shift); - - /* Set control register value. */ - register_table->control = - (mode->vertical_sync_polarity == POSITIVE ? - FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_HIGH) : - FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW)) | - (mode->horizontal_sync_polarity == POSITIVE ? - FIELD_SET(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_HIGH) : - FIELD_SET(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW)) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE) | - FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE) | - (bpp == 8 ? - FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 8) : - (bpp == 16 ? - FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 16) : - FIELD_SET(0, PANEL_DISPLAY_CTRL, FORMAT, 32))); - - /* Set timing registers. */ - register_table->horizontal_total = - FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, - mode->horizontal_total - 1) | - FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END, - mode->horizontal_display_end - 1); - - register_table->horizontal_sync = - FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, - mode->horizontal_sync_width) | - FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, - mode->horizontal_sync_start - 1); - - register_table->vertical_total = - FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, - mode->vertical_total - 1) | - FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, - mode->vertical_display_end - 1); - - register_table->vertical_sync = - FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, - mode->vertical_sync_height) | - FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, - mode->vertical_sync_start - 1); - } - else { - /* Set clock value for CRT. */ - register_table->clock = - (clock.mclk == 288000000 ? - FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_SELECT, 288) : - FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_SELECT, 336)) | - (clock.divider == 1 ? - FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_DIVIDER, 1) : - FIELD_SET(0, CURRENT_POWER_CLOCK, V2XCLK_DIVIDER, 3)) | - FIELD_VALUE(0, CURRENT_POWER_CLOCK, V2XCLK_SHIFT, clock.shift); - - /* Set control register value.*/ - register_table->control = - (mode->vertical_sync_polarity == POSITIVE ? - FIELD_SET(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_HIGH) : - FIELD_SET(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, ACTIVE_LOW)) | - (mode->horizontal_sync_polarity == POSITIVE ? - FIELD_SET(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_HIGH) : - FIELD_SET(0, CRT_DISPLAY_CTRL, HSYNC_PHASE, ACTIVE_LOW)) | - FIELD_SET(0, CRT_DISPLAY_CTRL, SELECT, CRT) | - FIELD_SET(0, CRT_DISPLAY_CTRL, TIMING, ENABLE) | - FIELD_SET(0, CRT_DISPLAY_CTRL, PLANE, ENABLE) | - (bpp == 8 ? - FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 8) : - (bpp == 16 ? - FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 16) : - FIELD_SET(0, CRT_DISPLAY_CTRL, FORMAT, 32))); - - /* Set timing registers. */ - register_table->horizontal_total = - FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, - mode->horizontal_total - 1) | - FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, - mode->horizontal_display_end - 1); - - register_table->horizontal_sync = - FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH, - mode->horizontal_sync_width) | - FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START, - mode->horizontal_sync_start - 1); - - register_table->vertical_total = - FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL, - mode->vertical_total - 1) | - FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END, - mode->vertical_display_end - 1); - register_table->vertical_sync = - FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, - mode->vertical_sync_height) | - FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, - mode->vertical_sync_start - 1); - } + field(mode->panel_wwidth, x) = 0; + field(mode->panel_wwidth, width) = xf86mode->HDisplay; - /* Set up framebuffer pitch, from passed in value */ - register_table->fb_width = mode->horizontal_display_end * (bpp / 8); - register_table->fb_width = fbPitch; + field(mode->panel_wheight, y) = 0; + field(mode->panel_wheight, height) = xf86mode->VDisplay; - /* Calculate frame buffer width and height. */ - register_table->width = mode->horizontal_display_end; - register_table->height = mode->vertical_display_end; + field(mode->panel_plane_tl, top) = 0; + field(mode->panel_plane_tl, left) = 0; - /* Save display type. */ - register_table->display = display; -} + field(mode->panel_plane_br, right) = xf86mode->HDisplay - 1; + field(mode->panel_plane_br, bottom) = xf86mode->VDisplay - 1; -/* Program the mode with the registers specified. */ -static void -programMode(SMIPtr pSmi, reg_table_t *register_table) -{ - unsigned int value, gate, clock; - unsigned int palette_ram; - unsigned int fb_size, offset; - - /* Get current power configuration. */ - gate = SMI501_Read32(pSmi, CURRENT_POWER_GATE); - gate |= 0x08; /* Enable power to 2D engine */ - gate = FIELD_SET(gate, CURRENT_POWER_GATE, CSC, ENABLE); - gate = FIELD_SET(gate, CURRENT_POWER_GATE, ZVPORT, ENABLE); - gate = FIELD_SET(gate, CURRENT_POWER_GATE, GPIO_PWM_I2C, ENABLE); - - clock = SMI501_Read32(pSmi, CURRENT_POWER_CLOCK); - - clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SELECT, 336); - clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_DIVIDER, 3); - clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, MCLK_SHIFT, 0); - clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SELECT, 336); - clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_DIVIDER, 1); - clock = FIELD_SET(clock, CURRENT_POWER_CLOCK, M2XCLK_SHIFT, 1); - - /* Program panel. */ - if (register_table->display == PANEL) { - /* Program clock, enable display controller. */ - gate = FIELD_SET(gate, CURRENT_POWER_GATE, DISPLAY, ENABLE); - clock &= FIELD_CLEAR(CURRENT_POWER_CLOCK, P2XCLK_SELECT) & - FIELD_CLEAR(CURRENT_POWER_CLOCK, P2XCLK_DIVIDER) & - FIELD_CLEAR(CURRENT_POWER_CLOCK, P2XCLK_SHIFT); - setPower(pSmi, gate, clock | register_table->clock); - - /* Calculate frame buffer address. */ - value = 0; - fb_size = register_table->fb_width * register_table->height; - if (FIELD_GET(SMI501_Read32(pSmi, CRT_DISPLAY_CTRL), - CRT_DISPLAY_CTRL, - PLANE) == CRT_DISPLAY_CTRL_PLANE_ENABLE) { - value = FIELD_GET(SMI501_Read32(pSmi, CRT_FB_ADDRESS), - CRT_FB_ADDRESS, ADDRESS); - if (fb_size < value) - value = 0; - else - value += FIELD_GET(SMI501_Read32(pSmi, CRT_FB_WIDTH), - CRT_FB_WIDTH, OFFSET) * - (FIELD_GET(SMI501_Read32(pSmi, CRT_VERTICAL_TOTAL), - CRT_VERTICAL_TOTAL, DISPLAY_END) + 1); - } + /* 0 means pulse high */ + field(mode->panel_display_ctl, hsync) = !(xf86mode->Flags & V_PHSYNC); + field(mode->panel_display_ctl, vsync) = !(xf86mode->Flags & V_PVSYNC); - /* Program panel registers. */ - SMI501_Write32(pSmi, PANEL_FB_ADDRESS, - FIELD_SET(0, PANEL_FB_ADDRESS, STATUS, PENDING) | - FIELD_SET(0, PANEL_FB_ADDRESS, EXT, LOCAL) | - FIELD_VALUE(0, PANEL_FB_ADDRESS, ADDRESS, value)); - - SMI501_Write32(pSmi, PANEL_FB_WIDTH, - FIELD_VALUE(0, PANEL_FB_WIDTH, WIDTH, - register_table->fb_width) | - FIELD_VALUE(0, PANEL_FB_WIDTH, OFFSET, - register_table->fb_width)); - - SMI501_Write32(pSmi, PANEL_WINDOW_WIDTH, - FIELD_VALUE(0, PANEL_WINDOW_WIDTH, WIDTH, - register_table->width) | - FIELD_VALUE(0, PANEL_WINDOW_WIDTH, X, 0)); - - SMI501_Write32(pSmi, PANEL_WINDOW_HEIGHT, - FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, HEIGHT, - register_table->height) | - FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, Y, 0)); - - SMI501_Write32(pSmi, PANEL_PLANE_TL, - FIELD_VALUE(0, PANEL_PLANE_TL, TOP, 0) | - FIELD_VALUE(0, PANEL_PLANE_TL, LEFT, 0)); - - SMI501_Write32(pSmi, PANEL_PLANE_BR, - FIELD_VALUE(0, PANEL_PLANE_BR, BOTTOM, - register_table->height - 1) | - FIELD_VALUE(0, PANEL_PLANE_BR, RIGHT, - register_table->width - 1)); - - SMI501_Write32(pSmi, PANEL_HORIZONTAL_TOTAL, - register_table->horizontal_total); - SMI501_Write32(pSmi, PANEL_HORIZONTAL_SYNC, - register_table->horizontal_sync); - SMI501_Write32(pSmi, PANEL_VERTICAL_TOTAL, - register_table->vertical_total); - SMI501_Write32(pSmi, PANEL_VERTICAL_SYNC, - register_table->vertical_sync); - - /* Program panel display control register. */ - value = SMI501_Read32(pSmi, PANEL_DISPLAY_CTRL) & - FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE) & - FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE) & - FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING) & - FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE) & - FIELD_CLEAR(PANEL_DISPLAY_CTRL, FORMAT); - - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, value | - register_table->control); - - /* Palette RAM. */ - palette_ram = PANEL_PALETTE_RAM; - - /* Turn on panel. */ - panelPowerSequence(pSmi, PANEL_ON, 4); - - SMI501_Write32(pSmi, MISC_CTRL, - FIELD_SET(SMI501_Read32(pSmi, MISC_CTRL), MISC_CTRL, - DAC_POWER, ENABLE)); - SMI501_Write32(pSmi, CRT_DISPLAY_CTRL, - FIELD_SET(SMI501_Read32(pSmi, CRT_DISPLAY_CTRL), - CRT_DISPLAY_CTRL, SELECT, PANEL)); - } + field(mode->panel_htotal, total) = xf86mode->HTotal - 1; + field(mode->panel_htotal, end) = xf86mode->HDisplay - 1; - /* Program CRT. */ - else { - /* Program clock, enable display controller. */ - gate = FIELD_SET(gate, CURRENT_POWER_GATE, DISPLAY, ENABLE); - clock &= FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SELECT) & - FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_DIVIDER) & - FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SHIFT); - - setPower(pSmi, gate, clock | register_table->clock); - - /* Turn on DAC. */ - SMI501_Write32(pSmi, MISC_CTRL, FIELD_SET(SMI501_Read32(pSmi, MISC_CTRL), - MISC_CTRL, DAC_POWER, ENABLE)); - - /* Calculate frame buffer address. */ - value = 0; - fb_size = register_table->fb_width * register_table->height; - if (FIELD_GET(SMI501_Read32(pSmi, PANEL_DISPLAY_CTRL), - PANEL_DISPLAY_CTRL, - PLANE) == PANEL_DISPLAY_CTRL_PLANE_ENABLE) { - value = FIELD_GET(SMI501_Read32(pSmi, PANEL_FB_ADDRESS), - PANEL_FB_ADDRESS, ADDRESS); - if (fb_size < value) - value = 0; - else - value += FIELD_GET(SMI501_Read32(pSmi, PANEL_FB_WIDTH), - PANEL_FB_WIDTH, OFFSET) * - FIELD_GET(SMI501_Read32(pSmi, PANEL_WINDOW_HEIGHT), - PANEL_WINDOW_HEIGHT, HEIGHT); - } + field(mode->panel_hsync, start) = xf86mode->HSyncStart; + field(mode->panel_hsync, width) = xf86mode->HSyncEnd - + xf86mode->HSyncStart; - /* Program CRT registers. */ - SMI501_Write32(pSmi, CRT_FB_ADDRESS, - FIELD_SET(0, CRT_FB_ADDRESS, STATUS, PENDING) | - FIELD_SET(0, CRT_FB_ADDRESS, EXT, LOCAL) | - FIELD_VALUE(0, CRT_FB_ADDRESS, ADDRESS, value)); - - SMI501_Write32(pSmi, CRT_FB_WIDTH, - FIELD_VALUE(0, CRT_FB_WIDTH, WIDTH, - register_table->fb_width) | - FIELD_VALUE(0, CRT_FB_WIDTH, OFFSET, - register_table->fb_width)); - - SMI501_Write32(pSmi, CRT_HORIZONTAL_TOTAL, - register_table->horizontal_total); - SMI501_Write32(pSmi, CRT_HORIZONTAL_SYNC, - register_table->horizontal_sync); - SMI501_Write32(pSmi, CRT_VERTICAL_TOTAL, - register_table->vertical_total); - SMI501_Write32(pSmi, CRT_VERTICAL_SYNC, - register_table->vertical_sync); - - /* Program CRT display control register. */ - value = SMI501_Read32(pSmi, CRT_DISPLAY_CTRL) & - FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE) & - FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE) & - FIELD_CLEAR(CRT_DISPLAY_CTRL, SELECT) & - FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING) & - FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE) & - FIELD_CLEAR(CRT_DISPLAY_CTRL, FORMAT); - - SMI501_Write32(pSmi, CRT_DISPLAY_CTRL, value | register_table->control); - - /* Palette RAM. */ - palette_ram = CRT_PALETTE_RAM; - - /* Turn on CRT. */ - SMI501_SetDPMS(pSmi, DPMS_ON); - } + field(mode->panel_vtotal, total) = xf86mode->VTotal - 1; + field(mode->panel_vtotal, end) = xf86mode->VDisplay - 1; - /* In case of 8-bpp, fill palette. */ - if (FIELD_GET(register_table->control, - PANEL_DISPLAY_CTRL, - FORMAT) == PANEL_DISPLAY_CTRL_FORMAT_8) { - /* Start with RGB = 0,0,0. */ - BYTE red = 0, green = 0, blue = 0; - unsigned int gray = 0; - - for (offset = 0; offset < 256 * 4; offset += 4) { - /* Store current RGB value. */ - /* ERROR!!!!! IGX RGB should be a function, maybe RGB16? - SMI501_Write32(pSmi, (palette_ram + offset), - (gray ? (RGB((gray + 50) / 100, - (gray + 50) / 100, - (gray + 50) / 100)) - : (RGB(red, green, blue)))); - */ - - if (gray) /* Walk through grays (40 in total). */ - gray += 654; - else { /* Walk through colors (6 per base color). */ - if (blue != 255) - blue += 51; - else if (green != 255) { - blue = 0; - green += 51; - } - else if (red != 255) { - green = blue = 0; - red += 51; - } - else - gray = 1; - } - } + field(mode->panel_vsync, start) = xf86mode->VSyncStart; + field(mode->panel_vsync, height) = xf86mode->VSyncEnd - + xf86mode->VSyncStart; } - - /* For 16- and 32-bpp, fill palette with gamma values. */ else { - /* Start with RGB = 0,0,0. */ - value = 0x000000; - for (offset = 0; offset < 256 * 4; offset += 4) { - SMI501_Write32(pSmi, palette_ram + offset, value); - /* Advance RGB by 1,1,1. */ - value += 0x010101; - } + field(mode->clock, v2_select) = mclk == 288000.0 ? 0 : 1; + clock = mode->clock.value; + field(mode->clock, v2_divider) = x2_divider; + field(mode->clock, v2_shift) = x2_shift; + SMI501_SetClock(pSmi, mode->current_clock, clock, mode->clock.value); + + field(mode->crt_display_ctl, format) = + pScrn->bitsPerPixel == 8 ? 0 : + pScrn->bitsPerPixel == 16 ? 1 : 2; + + /* 0: select panel - 1: select crt */ + field(mode->crt_display_ctl, select) = 1; + field(mode->crt_display_ctl, enable) = 1; + + /* FIXME if non clone dual head, and secondary, need to + * properly set crt fb address properly ... */ + field(mode->crt_fb_address, address) = 0; + field(mode->crt_fb_address, mextern) = 0; /* local memory */ + field(mode->crt_fb_address, pending) = 0; /* FIXME required? */ + + /* >> 4 because of the "unused fields" that should be set to 0 */ + /* FIXME this should be used for virtual size? */ + field(mode->crt_fb_width, offset) = pSmi->Stride >> 4; + field(mode->crt_fb_width, width) = pSmi->Stride >> 4; + + /* 0 means pulse high */ + field(mode->crt_display_ctl, hsync) = !(xf86mode->Flags & V_PHSYNC); + field(mode->crt_display_ctl, vsync) = !(xf86mode->Flags & V_PVSYNC); + + field(mode->crt_htotal, total) = xf86mode->HTotal - 1; + field(mode->crt_htotal, end) = xf86mode->HDisplay - 1; + + field(mode->crt_hsync, start) = xf86mode->HSyncStart; + field(mode->crt_hsync, width) = xf86mode->HSyncEnd - + xf86mode->HSyncStart; + + field(mode->crt_vtotal, total) = xf86mode->VTotal - 1; + field(mode->crt_vtotal, end) = xf86mode->VDisplay - 1; + + field(mode->crt_vsync, start) = xf86mode->HSyncStart; + field(mode->crt_vsync, height) = xf86mode->HSyncEnd - + xf86mode->HSyncStart; } -} -static void -SetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, - unsigned int fMode, unsigned int nHertz, display_t display, - int fbPitch, int bpp) -{ - mode_table_t mode; - pmode_table_t vesaMode; - reg_table_t register_table; + WRITE_SCR(pSmi, MISC_CTL, mode->misc_ctl.value); - /* Locate the mode */ - vesaMode = findMode(mode_table, nWidth, nHeight, nHertz); + if (pSmi->lcd) { + WRITE_SCR(pSmi, PANEL_FB_ADDRESS, mode->panel_fb_address.value); + WRITE_SCR(pSmi, PANEL_FB_WIDTH, mode->panel_fb_width.value); - if (vesaMode != NULL) { - /* Convert VESA timing into Voyager timing */ - adjustMode(vesaMode, &mode, display); + WRITE_SCR(pSmi, PANEL_WWIDTH, mode->panel_wwidth.value); + WRITE_SCR(pSmi, PANEL_WHEIGHT, mode->panel_wheight.value); - /* Fill the register structure */ - setModeRegisters(®ister_table, &mode, display, bpp, fbPitch); + WRITE_SCR(pSmi, PANEL_PLANE_TL, mode->panel_plane_tl.value); + WRITE_SCR(pSmi, PANEL_PLANE_BR, mode->panel_plane_br.value); - /* Program the registers */ - programMode(pSmi, ®ister_table); - } -} + WRITE_SCR(pSmi, PANEL_HTOTAL, mode->panel_htotal.value); + WRITE_SCR(pSmi, PANEL_HSYNC, mode->panel_hsync.value); + WRITE_SCR(pSmi, PANEL_VTOTAL, mode->panel_vtotal.value); + WRITE_SCR(pSmi, PANEL_VSYNC, mode->panel_vsync.value); + WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value); -static void -panelSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, - unsigned int fMode, unsigned int nHertz, int fbPitch, int bpp) -{ - SetMode(pSmi, nWidth, nHeight, fMode, 60 /* was nHertz */, PANEL, - fbPitch, bpp); -} + /* Power up sequence for panel */ + field(mode->panel_display_ctl, vdd) = 1; + WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value); + SMI501_WaitVSync(pSmi, 4); -static void -crtSetMode(SMIPtr pSmi, unsigned int nWidth, unsigned int nHeight, - unsigned int fMode, unsigned int nHertz, int fbPitch, int bpp) -{ - SetMode(pSmi, nWidth, nHeight, fMode, nHertz, CRT, - fbPitch, bpp); -} + field(mode->panel_display_ctl, signal) = 1; + WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value); + SMI501_WaitVSync(pSmi, 4); -/* - * - * - * From POWER.C - * - * - */ -/* Program new power mode. */ -static void -setPower(SMIPtr pSmi, unsigned int nGates, unsigned int Clock) -{ - unsigned int gate_reg, clock_reg; - unsigned int control_value; + field(mode->panel_display_ctl, bias) = 1; + WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value); + SMI501_WaitVSync(pSmi, 4); - /* Get current power mode. */ - control_value = FIELD_GET(SMI501_Read32(pSmi, POWER_MODE_CTRL), - POWER_MODE_CTRL, MODE); + field(mode->panel_display_ctl, fp) = 1; + WRITE_SCR(pSmi, PANEL_DISPLAY_CTL, mode->panel_display_ctl.value); + SMI501_WaitVSync(pSmi, 4); - switch (control_value) { - case POWER_MODE_CTRL_MODE_MODE0: + /* FIXME: No dual head setup, and in this case, crt may + * just be another panel */ + /* crt clones panel */ + field(mode->crt_display_ctl, enable) = 1; + /* 0: select panel - 1: select crt */ + field(mode->crt_display_ctl, select) = 0; + WRITE_SCR(pSmi, CRT_DISPLAY_CTL, mode->crt_display_ctl.value); + } + else { + WRITE_SCR(pSmi, CRT_FB_ADDRESS, mode->crt_fb_address.value); + WRITE_SCR(pSmi, CRT_FB_WIDTH, mode->crt_fb_width.value); + WRITE_SCR(pSmi, CRT_HTOTAL, mode->crt_htotal.value); + WRITE_SCR(pSmi, CRT_HSYNC, mode->crt_hsync.value); + WRITE_SCR(pSmi, CRT_VTOTAL, mode->crt_vtotal.value); + WRITE_SCR(pSmi, CRT_VSYNC, mode->crt_vsync.value); + WRITE_SCR(pSmi, CRT_DISPLAY_CTL, mode->crt_display_ctl.value); + + /* Turn CRT on */ + SMI501_DisplayPowerManagementSet(pScrn, DPMSModeOn, 0); + } - /* Switch from mode 0 to mode 1. */ - gate_reg = POWER_MODE1_GATE; - clock_reg = POWER_MODE1_CLOCK; - control_value = FIELD_SET(control_value, - POWER_MODE_CTRL, MODE, MODE1); - break; + WRITE_SCR(pSmi, POWER_CTL, mode->power_ctl.value); - case POWER_MODE_CTRL_MODE_MODE1: - case POWER_MODE_CTRL_MODE_SLEEP: + /* FIXME update pallete here if running at 8 bpp */ - /* Switch from mode 1 or sleep to mode 0. */ - gate_reg = POWER_MODE0_GATE; - clock_reg = POWER_MODE0_CLOCK; - control_value = FIELD_SET(control_value, - POWER_MODE_CTRL, MODE, MODE0); - break; + SMI_AdjustFrame(pScrn->scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); - default: - /* Invalid mode */ - return; + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, VERBLEV, + "Register dump (After Mode Init)\n"); + SMI501_PrintRegs(pScrn); + + return (TRUE); +} + +static char * +format_integer_base2(int32_t word) +{ + int i; + static char buffer[33]; + + for (i = 0; i < 32; i++) { + if (word & (1 << i)) + buffer[31 - i] = '1'; + else + buffer[31 - i] = '0'; } - /* Program new power mode. */ - SMI501_Write32(pSmi, gate_reg, nGates); - SMI501_Write32(pSmi, clock_reg, Clock); - SMI501_Write32(pSmi, POWER_MODE_CTRL, control_value); - - /* When returning from sleep, wait until finished. */ - /* IGX -- comment out for now, gets us in an infinite loop! - while (FIELD_GET(SMI501_Read32(pSmi, POWER_MODE_CTRL), - POWER_MODE_CTRL, - SLEEP_STATUS) == POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE) ; - */ + return (buffer); +} + +static void +SMI501_PrintRegs(ScrnInfoPtr pScrn) +{ + int i; + SMIPtr pSmi = SMIPTR(pScrn); + + xf86ErrorFVerb(VERBLEV, " SMI501 System Setup:\n"); + for (i = 0x00; i < 0x6c; i += 4) + xf86ErrorFVerb(VERBLEV, "\t%08x: %s\n", i, + format_integer_base2(READ_SCR(pSmi, i))); + xf86ErrorFVerb(VERBLEV, " SMI501 Display Setup:\n"); + for (i = 0x80000; i < 0x80400; i += 4) + xf86ErrorFVerb(VERBLEV, "\t%08x: %s\n", i, + format_integer_base2(READ_SCR(pSmi, i))); } -/* Panel Code */ -/********************************************************************** - * - * panelWaitVSync - * - * Purpose - * Wait for the specified number of panel Vsyncs - * - * Parameters - * [in] - * vsync_count - Number of Vsyncs to wait - * - * [out] - * None - * - * Returns - * Nothing - * - **********************************************************************/ static void -panelWaitVSync(SMIPtr pSmi, int vsync_count) +SMI501_WaitVSync(SMIPtr pSmi, int vsync_count) { - unsigned int status; - unsigned int timeout; + int32_t status, timeout; while (vsync_count-- > 0) { /* Wait for end of vsync */ timeout = 0; do { - status = FIELD_GET(SMI501_Read32(pSmi, CMD_INTPR_STATUS), - CMD_INTPR_STATUS, PANEL_SYNC); - if (++timeout == VSYNCTIMEOUT) + /* bit 11: vsync active *if set* */ + status = READ_SCR(pSmi, CMD_STATUS); + if (++timeout == 10000) break; - } while (status == CMD_INTPR_STATUS_PANEL_SYNC_ACTIVE); + } while (status & (1 << 11)); /* Wait for start of vsync */ timeout = 0; do { - status = FIELD_GET(SMI501_Read32(pSmi, CMD_INTPR_STATUS), - CMD_INTPR_STATUS, PANEL_SYNC); - if (++timeout == VSYNCTIMEOUT) + status = READ_SCR(pSmi, CMD_STATUS); + if (++timeout == 10000) break; - } while (status == CMD_INTPR_STATUS_PANEL_SYNC_INACTIVE); - } -} - -/********************************************************************** - * - * panelPowerSequence - * - * Purpose - * Turn the panel On/Off - * - * Parameters - * [in] - * on_off - Turn panel On/Off. Can be: - * PANEL_ON - * PANEL_OFF - * vsync_delay - Number of Vsyncs to wait after each signal is - * turned on/off - * - * [out] - * None - * - * Returns - * Nothing - * - **********************************************************************/ -static void -panelPowerSequence(SMIPtr pSmi, panel_state_t on_off, int vsync_delay) -{ - unsigned int panelControl = SMI501_Read32(pSmi, PANEL_DISPLAY_CTRL); - - if (on_off == PANEL_ON) { - /* Turn on FPVDDEN. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, FPVDDEN, HIGH); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - panelWaitVSync(pSmi, vsync_delay); - - /* Turn on FPDATA. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, DATA, ENABLE); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - panelWaitVSync(pSmi, vsync_delay); - - /* Turn on FPVBIAS. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, VBIASEN, HIGH); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - panelWaitVSync(pSmi, vsync_delay); - - /* Turn on FPEN. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, FPEN, HIGH); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - } - else { - /* Turn off FPEN. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, FPEN, LOW); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - panelWaitVSync(pSmi, vsync_delay); - - /* Turn off FPVBIASEN. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, VBIASEN, LOW); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - panelWaitVSync(pSmi, vsync_delay); - - /* Turn off FPDATA. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, DATA, DISABLE); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); - panelWaitVSync(pSmi, vsync_delay); - - /* Turn off FPVDDEN. */ - panelControl = FIELD_SET(panelControl, - PANEL_DISPLAY_CTRL, FPVDDEN, LOW); - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panelControl); + } while (!(status & (1 << 11))); } } -/********************************************************************** - * - * panelUseCRT - * - * Purpose - * Enable/disable routing of panel output to CRT monitor - * - * Parameters - * [in] - * bEnable - TRUE enables routing of panel output to CRT monitor - * FALSE disables routing of panel output to CRT monitor - * - * [out] - * None - * - * Returns - * Nothing - * - **********************************************************************/ static void -panelUseCRT(SMIPtr pSmi, BOOL bEnable) -{ - unsigned int panel_ctrl = 0; - unsigned int crt_ctrl = 0; - - panel_ctrl = SMI501_Read32(pSmi, PANEL_DISPLAY_CTRL); - crt_ctrl = SMI501_Read32(pSmi, CRT_DISPLAY_CTRL); - - if (bEnable) { - /* Enable panel graphics plane */ - panel_ctrl = FIELD_SET(panel_ctrl, PANEL_DISPLAY_CTRL, PLANE, ENABLE); - - /* Disable CRT graphics plane */ - crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, PLANE, DISABLE); - - /* Route panel data to CRT monitor */ - crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, SELECT, PANEL); - } - else { - /* Disable panel graphics plane */ - panel_ctrl = FIELD_SET(panel_ctrl, PANEL_DISPLAY_CTRL, PLANE, DISABLE); - - /* Enable CRT graphics plane */ - crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, PLANE, ENABLE); - - /* Do not route panel data to CRT monitor */ - crt_ctrl = FIELD_SET(crt_ctrl, CRT_DISPLAY_CTRL, SELECT, CRT); - } - - SMI501_Write32(pSmi, PANEL_DISPLAY_CTRL, panel_ctrl); - SMI501_Write32(pSmi, CRT_DISPLAY_CTRL, crt_ctrl); -} - -void -DisableOverlay(SMIPtr pSmi) -{ - int dwVal = READ_VPR(pSmi, 0x00); - - WRITE_VPR(pSmi, 0x00, dwVal & 0xfffffffb); -} -void -EnableOverlay(SMIPtr pSmi) +SMI501_SetClock(SMIPtr pSmi, int32_t port, int32_t clock, int32_t value) { - int dwVal = READ_VPR(pSmi, 0x00); - - WRITE_VPR(pSmi, 0x00, dwVal | 0x00000004); + /* + * Rules to Program the Power Mode Clock Registers for Clock Selection + * + * 1. There should be only one clock source changed at a time. + * To change clock source for P2XCLK, V2XCLK, MCLK, M2XCLK + * simultaneously may cause the internal logic normal operation + * to be disrupted. There should be a minimum of 16mS wait from + * change one clock source to another. + * 2. When adjusting the clock rate, the PLL selection bit should + * be programmed first before changing the divider value for each + * clock source. For example, to change the P2XCLK clock rate: + * . bit 29 should be set first + * . wait for a minimum of 16ms (about one Vsync time) + * . adjust bits [28:24]. + * The minimum 16 ms wait is necessary for logic to settle down + * before the clock rate is changed. + * 3. There should be a minimum 16 ms wait after a clock source is + * changed before any operation that could result in a bus + * transaction. + */ + + /* register contents selecting clock */ + WRITE_SCR(pSmi, port, clock); + SMI501_WaitVSync(pSmi, 1); + + /* full register contents */ + WRITE_SCR(pSmi, port, clock); + SMI501_WaitVSync(pSmi, 1); } diff --git a/src/smi_501.h b/src/smi_501.h index 06cb1d3..f49630a 100644 --- a/src/smi_501.h +++ b/src/smi_501.h @@ -1,8 +1,7 @@ -/* Header: //Mercury/Projects/archives/XFree86/4.0/smi.h-arc 1.51 29 Nov 2000 17:45:16 Frido $ */ - /* Copyright (C) 1994-1999 The XFree86 Project, Inc. All Rights Reserved. Copyright (C) 2000 Silicon Motion, Inc. All Rights Reserved. +Copyright (C) 2008 Mandriva Linux. All Rights Reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in @@ -26,1249 +25,674 @@ Silicon Motion shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the XFree86 Project and Silicon Motion. */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/siliconmotion/smi.h,v 1.13 2003/04/23 21:51:44 tsi Exp $ */ #ifndef _SMI_501_H #define _SMI_501_H +/* + * Documentation: + * ftp://ftp.siliconmotion.com.tw/databooks/SM501MSOCDatabook_VersionB_1.pdf + */ + +#include <stdint.h> + +#define field(record, name) record.detail.name +#define bitfield(lo, hi) hi + 1 - lo + + +#define DRAM_CONTROL 0x000010 +#define CMD_STATUS 0x000024 + +/* contents of either power0_clock or power1_clock */ +#define CURRENT_CLOCK 0x00003c + +typedef struct _MSOCRegRec { +#define SYSTEM_CTL 0x000000 + /* SYSTEM CONTROL + * Read/Write MMIO_base + 0x000000 + * Power-on Default 0b0000.0000.XX0X.X0XX.0000.0000.0000.0000 + * + * 30:31 Vertical Sync Horizontal Sync + * 00 Pulsing Pulsing + * 01 Pulsing Not pulsing + * 10 Not pulsing Pulsing + * 11 Not pulsing Not pulsing + */ + union { + struct { + int32_t u0 : bitfield( 0, 29); + int32_t dpmsh : bitfield(30, 30); + int32_t dpmsv : bitfield(31, 31); + } detail; + int32_t value; + } system_ctl; + +#define MISC_CTL 0x000004 + /* Miscellaneous Control + * Read/Write MMIO_base + 0x000004 + * Power-on Default 0b0000.0000.0000.00X0.0001.0000.XXX0.0XXX + * + * 12:12 DAC Power Control. + * 0: Enable. + * 1: Disable. + */ + union { + struct { + int32_t u0 : bitfield( 0, 11); + int32_t dac : bitfield(12, 12); + } detail; + int32_t value; + } misc_ctl; + +#define POWER0_GATE 0x000040 +#define POWER1_GATE 0x000048 + /* POWER MODE 0 GATE + * Read/Write MMIO_base + 0x000040 + * Power-on Default 0x00021807 + * + * POWER MODE 1 GATE + * Read/Write MMIO_base + 0x000048 + * Power-on Default 0x00021807 + * + * 3:3 2D Engine Clock Control. + * 0: Disable. + * 1: Enable. + * 4:4 Color Space Conversion Clock Control. + * 0: Disable. + * 1: Enable. + * 5:5 ZV-Port Clock Control. + * 0: Disable. + * 1: Enable. + * 6:6 GPIO, PWM, and I2C Clock Control. + * 0: Disable. + * 1: Enable. + */ + union { + struct { + int32_t u0 : bitfield(0, 2); + int32_t engine : bitfield(3, 3); + int32_t csc : bitfield(4, 4); + int32_t zv : bitfield(5, 5); + int32_t gpio : bitfield(6, 6); + } detail; + int32_t value; + } gate; + int32_t current_gate; + +#define POWER0_CLOCK 0x000044 +#define POWER1_CLOCK 0x00004c + /* POWER MODE 0 CLOCK + * Read/Write MMIO_base + 0x000044 + * Power-on Default 0x2A1A0A09 + * + * POWER MODE 1 CLOCK + * Read/Write MMIO_base + 0x00004C + * Power-on Default 0x2A1A0A09 + * + * 0:3 M2XCLK Frequency Divider + * 0000 / 1 1000 / 3 + * 0001 / 2 1001 / 6 + * 0010 / 4 1010 / 12 + * 0011 / 8 1011 / 24 + * 0100 / 16 1100 / 48 + * 0101 / 32 1101 / 96 + * 0110 / 64 1110 / 192 + * 0111 / 128 1111 / 384 + * 4:4 M2XCLK Frequency Input Select. + * 0: 288 MHz. + * 1: 336 MHz/288 MHz/240 MHz/192 MHz + * (see bits 5:4 in the Miscellaneous Timing register + * at offset 0x68 on page 2-42). + * 8:11 MCLK Frequency Divider. + * 0000 / 1 1000 / 3 + * 0001 / 2 1001 / 6 + * 0010 / 4 1010 / 12 + * 0011 / 8 1011 / 24 + * 0100 / 16 1100 / 48 + * 0101 / 32 1101 / 96 + * 0110 / 64 1110 / 192 + * 0111 / 128 1111 / 384 + * 12:12 MCLK Frequency Input Select. + * 0: 288 MHz. + * 1: 336 MHz/288 MHz/240 MHz/192 MHz + * (see bits 5:4 in the Miscellaneous Timing register + * at offset 0x68 on page 2-42). + * 16:19 V2XCLK DIVIDER + * 0000 / 1 1000 / 3 + * 0001 / 2 1001 / 6 + * 0010 / 4 1010 / 12 + * 0011 / 8 1011 / 24 + * 0100 / 16 1100 / 48 + * 0101 / 32 1101 / 96 + * 0110 / 64 1110 / 192 + * 0111 / 128 1111 / 384 + * 20:20 V2XCLK SELECT (Crt clock) + * 0: 288 MHz + * 1: 336 MHz/288 MHz/240 MHz/192 MHz + * (see bits 5:4 in the Miscellaneous Timing register + * at offset 0x68 on page 2-42). + * 24:28 P2XCLK DIVIDER + * 00000 / 1 01000 / 3 10000 / 5 + * 00001 / 2 01001 / 6 10001 / 10 + * 00010 / 4 01010 / 12 10010 / 20 + * 00011 / 8 01011 / 24 10011 / 40 + * 00100 / 16 01100 / 48 10100 / 80 + * 00101 / 32 01101 / 96 10101 / 160 + * 00110 / 64 01110 / 192 10110 / 320 + * 00111 / 128 01111 / 384 10111 / 640 + * 29:29 P2XCLK SELECT (Panel clock) + * 0: 288 MHz + * 1: 336 MHz/288 MHz/240 MHz/192 MHz + * (see bits 5:4 in the Miscellaneous Timing register + * at offset 0x68 on page 2-42). + * + * Remarks: + * Table 2-2: Programmable Clock Branches + * Clock Description + * P2XCLK 2X clock source for the Panel interface timing. + * The actual rate at which the pixels are shifted + * out is P2XCLK divided by two. + * V2XCLK 2X clock source for the CRT interface timing. + * The actual rate at which the pixels are shifted + * out is V2XCLK divided by two + */ + union { + struct { + int32_t m2_shift : bitfield( 0, 2); + int32_t m2_divider : bitfield( 3, 3); + int32_t m2_select : bitfield( 4, 4); + int32_t u0 : bitfield( 5, 7); + int32_t m_shift : bitfield( 8, 10); + int32_t m_divider : bitfield(11, 11); + int32_t m_select : bitfield(12, 12); + int32_t u1 : bitfield(13, 15); + int32_t v2_shift : bitfield(16, 18); + int32_t v2_divider : bitfield(19, 19); + int32_t v2_select : bitfield(20, 20); + int32_t u2 : bitfield(21, 23); + int32_t p2_shift : bitfield(24, 26); + int32_t p2_divider : bitfield(27, 28); + int32_t p2_select : bitfield(29, 29); + } detail; + int32_t value; + } clock; + int32_t current_clock; + +#define SLEEP_GATE 0x000050 + /* SLEEP MODE GATE + * Read/Write MMIO_base + 0x000050 + * Power-on Default 0x00018000 + * + * 13:14 PLL Recovery. + * 00: 1ms (32 counts). + * 01: 2ms (64 counts). + * 10: 3ms (96 counts). + * 11: 4ms (128 counts). + * 19:22 PLL Recovery Clock Divider. + * 0000 / 4096 0100 / 256 1000 / 16 + * 0001 / 2048 0101 / 128 1001 / 8 + * 0010 / 1024 0110 / 64 1010 / 4 + * 0011 / 512 0111 / 32 1011 / 2 + * Internally, the PLL recovery time counters are based on a 32 us + * clock. So you have to program the D field (19:22) to make the + * host clock come as close to 33 us as possible. + */ + union { + struct { + int32_t u0 : bitfield( 0, 12); + int32_t recovery : bitfield(13, 14); + int32_t u1 : bitfield(15, 18); + int32_t divider : bitfield(19, 22); + } detail; + int32_t value; + } sleep_gate; + +#define POWER_CTL 0x000054 + /* POWER MODE CONTROL + * Read/Write MMIO_base + 0x000054 + * Power-on Default 0x00000000 + * + * 1:0 Power Mode Select. + * 00: Power Mode 0. + * 01: Power Mode 1. + * 10: Sleep Mode. + * 2:2 Current Sleep Status. + * 0: Not in sleep mode. + * 1: In sleep mode. + * When the SM501 is transitioning back from sleep mode to a normal + * power mode (Modes 0 or 1), the software needs to poll this bit + * until it becomes "0" before writing any other commands to the chip. + */ + union { + struct { + int32_t mode : bitfield(0, 1); + int32_t status : bitfield(2, 2); + } detail; + int32_t value; + } power_ctl; + + +#define TIMING_CONTROL 0x000068 + /* Miscellaneous Control + * Read/Write MMIO_base + 0x000068 + * Power-on Default 0x00000000 + * + * 4:5 PLL Input frequency + * 00: the output of PLL2 = 48 MHz x 7 = 336 MHz, power on default + * 01: the output of PLL2 = 48 MHz x 6 = 288 MHz + * 10: the output of PLL2 = 48 MHz x 5 = 240 MHz + * 11: the output of PLL2 = 48 MHz x 4 = 192 MHz + */ + union { + struct { + int32_t u0 : bitfield( 0, 3); + int32_t pll : bitfield( 4, 5); + } detail; + int32_t value; + } timing_control; + +#define PANEL_DISPLAY_CTL 0x080000 + /* PANEL DISPLAY CONTROL + * Read MMIO_base + 0x080000 + * Power-on Default 0x00010000 + * + * 1:0 Format Panel Graphics Plane Format. + * 00: 8-bit indexed mode. + * 01: 16-bit RGB 5:6:5 mode. + * 10: 32-bit RGB 8:8:8 mode. + * 2:2 Panel Graphics Plane Enable. + * 0: Disable panel graphics plane. + * 1: Enable panel graphics plane. + * 8:8 Enable Panel Timing. + * 0: Disable panel timing. + * 1: Enable panel timing. + * 12:12 Horizontal Sync Pulse Phase Select. + * 0: Horizontal sync pulse active high. + * 1: Horizontal sync pulse active low. + * 13:13 Vertical Sync Pulse Phase Select. + * 0: Vertical sync pulse active high. + * 1: Vertical sync pulse active low. + * 24:24 Control FPVDDEN Output Pin. + * 0: Driven low. + * 1: Driven high. + * 25:25 Panel Control Signals and Data Lines Enable. + * 0: Disable panel control signals and data lines. + * 1: Enable panel control signals and data lines. + * 26:26 Control VBIASEN Output Pin. + * 0: Driven low. + * 1: Driven high. + * 27:27 Control FPEN Output Pin. + * 0: Driven low. + * 1: Driven high. + */ + union { + struct { + int32_t format : bitfield( 0, 1); + int32_t enable : bitfield( 2, 2); + int32_t u0 : bitfield( 3, 7); + int32_t timing : bitfield( 8, 8); + int32_t u1 : bitfield( 9, 11); + int32_t hsync : bitfield(12, 12); + int32_t vsync : bitfield(13, 13); + int32_t u2 : bitfield(14, 23); + int32_t vdd : bitfield(24, 24); + int32_t signal : bitfield(25, 25); + int32_t bias : bitfield(26, 26); + int32_t fp : bitfield(27, 27); + } detail; + int32_t value; + } panel_display_ctl; + +#define PANEL_FB_ADDRESS 0x08000c + /* PANEL FB ADDRESS + * Read/Write MMIO_base + 0x08000C + * Power-on Default Undefined + * + * 4:25 Address Memory address of frame buffer for the + * panel graphics plane with 128-bit alignment. + * 26:26 Chip Select for External Memory. + * 0: CS0 of external memory. + * 1: CS1 of external memory. + * 27:27 Ext Memory Selection. + * 0: Local memory. + * 1: External memory. + * 31:31 Status Bit. + * 0: No flip pending. + * 1: Flip pending. + */ + union { + struct { + int32_t u0 : bitfield( 0, 3); + int32_t address : bitfield( 4, 25); + int32_t mextern : bitfield(26, 26); + int32_t mselect : bitfield(27, 27); + int32_t u1 : bitfield(28, 30); + int32_t pending : bitfield(31, 31); + } detail; + int32_t value; + } panel_fb_address; + +#define PANEL_FB_WIDTH 0x080010 + /* PANEL FB WIDTH + * Read/Write MMIO_base + 0x080010 + * Power-on Default Undefined + * + * 4:13 Number of 128-bit aligned bytes per line of the FB + * graphics plane + * 20:29 Number of bytes per line of the panel graphics window + * specified in 128-bit aligned bytes. + */ + union { + struct { + int32_t u0 : bitfield( 0, 3); + int32_t offset : bitfield( 4, 13); + int32_t u1 : bitfield(14, 19); + int32_t width : bitfield(20, 29); + } detail; + int32_t value; + } panel_fb_width; + +#define PANEL_WWIDTH 0x080014 + /* PANEL WINDOW WIDTH + * Read/Write MMIO_base + 0x080014 + * Power-on Default Undefined + * + * 0:11 Starting x-coordinate of panel graphics window + * specified in pixels. + * 16:27 Width of FB graphics window specified in pixels. + */ + union { + struct { + int32_t x : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t width : bitfield(16, 27); + } detail; + int32_t value; + } panel_wwidth; + +#define PANEL_WHEIGHT 0x080018 + /* PANEL WINDOW HEIGHT + * Read/Write MMIO_base + 0x080018 + * Power-on Default Undefined + * + * 0:11 Starting y-coordinate of panel graphics window + * specified in pixels. + * 16:27 Height of FB graphics window specified in pixels. + */ + union { + struct { + int32_t y : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t height : bitfield(16, 27); + } detail; + int32_t value; + } panel_wheight; + +#define PANEL_PLANE_TL 0x08001c + /* PANEL PLANE TL + * Read/Write MMIO_base + 0x08001c + * Power-on Default Undefined + * + * 0:10 Left location of the panel graphics plane specified in pixels. + * 16:26 Top location of the panel graphics plane specified in lines. + */ + union { + struct { + int32_t left : bitfield( 0, 10); + int32_t u0 : bitfield(11, 15); + int32_t top : bitfield(16, 26); + } detail; + int32_t value; + } panel_plane_tl; + +#define PANEL_PLANE_BR 0x080020 + /* PANEL PLANE BR + * Read/Write MMIO_base + 0x080020 + * Power-on Default Undefined + * + * 0:10 Right location of the panel graphics plane specified in pixels. + * 16:26 Bottom location of the panel graphics plane specified in lines. + */ + union { + struct { + int32_t right : bitfield( 0, 10); + int32_t u0 : bitfield(11, 15); + int32_t bottom : bitfield(16, 26); + } detail; + int32_t value; + } panel_plane_br; + +#define PANEL_HTOTAL 0x080024 + /* PANEL HORIZONTAL TOTAL + * Read/Write MMIO_base + 0x080024 + * Power-on Default Undefined + * + * 0:11 Panel horizontal display end specified as number of pixels - 1. + * 16:27 Panel horizontal total specified as number of pixels - 1. + */ + union { + struct { + int32_t end : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t total : bitfield(16, 27); + } detail; + int32_t value; + } panel_htotal; + +#define PANEL_HSYNC 0x080028 + /* PANEL HORIZONTAL SYNC + * Read/Write MMIO_base + 0x080028 + * Power-on Default Undefined + * + * 0:11 HS Panel horizontal sync start specified as pixel number - 1. + * 16:23 HSW Panel horizontal sync width specified in pixels. + */ + union { + struct { + int32_t start : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t width : bitfield(16, 23); + } detail; + int32_t value; + } panel_hsync; + +#define PANEL_VTOTAL 0x08002c + /* PANEL VERTICAL TOTAL + * Read/Write MMIO_base + 0x08002C + * Power-on Default Undefined + * + * 0:11 VDE Panel vertical display end specified as number of pixels - 1. + * 16:27 VT Panel vertical total specified as number of pixels - 1. + */ + union { + struct { + int32_t end : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t total : bitfield(16, 27); + } detail; + int32_t value; + } panel_vtotal; + +#define PANEL_VSYNC 0x080030 + /* PANEL VERTICAL SYNC + * Read/Write MMIO_base + 0x080030 + * Power-on Default Undefined + * + * 0:11 VS Panel vertical sync start specified as pixel number - 1. + * 16:23 VSH Panel vertical sync height specified in pixels. + */ + union { + struct { + int32_t start : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t height : bitfield(16, 23); + } detail; + int32_t value; + } panel_vsync; + +#define CRT_DISPLAY_CTL 0x080200 + /* CRT DISPLAY CONTROL + * Read MMIO_base + 0x080200 + * Power-on Default 0x00010000 + * + * 0:1 Format Panel Graphics Plane Format. + * 00: 8-bit indexed mode. + * 01: 16-bit RGB 5:6:5 mode. + * 10: 32-bit RGB 8:8:8 mode. + * 2:2 CRT Graphics Plane Enable. + * 0: Disable CRT Graphics plane. + * 1: Enable CRT Graphics plane. + * 9:9: CRT Data Select. + * 0: CRT will display panel data. + * 1: CRT will display CRT data. + * 12:12 Horizontal Sync Pulse Phase Select. + * 0: Horizontal sync pulse active high. + * 1: Horizontal sync pulse active low. + * 13:13 Vertical Sync Pulse Phase Select. + * 0: Vertical sync pulse active high. + * 1: Vertical sync pulse active low. + */ + union { + struct { + int32_t format : bitfield( 0, 1); + int32_t enable : bitfield( 2, 2); + int32_t u0 : bitfield( 3, 8); + int32_t select : bitfield( 9, 9); + int32_t u1 : bitfield(10, 11); + int32_t hsync : bitfield(12, 12); + int32_t vsync : bitfield(13, 13); + } detail; + int32_t value; + } crt_display_ctl; + +#define CRT_FB_ADDRESS 0x080204 + /* CRT FB ADDRESS + * Read/Write MMIO_base + 0x080204 + * Power-on Default Undefined + * + * 4:25 Address Memory address of frame buffer for the + * CRT graphics plane with 128-bit alignment. + * 26:26 Chip Select for External Memory. + * 0: CS0 of external memory. + * 1: CS1 of external memory. + * 27:27 Ext Memory Selection. + * 0: Local memory. + * 1: External memory. + * 31:31 Status Bit. + * 0: No flip pending. + * 1: Flip pending. + */ + union { + struct { + int32_t u0 : bitfield( 0, 3); + int32_t address : bitfield( 4, 25); + int32_t mextern : bitfield(26, 26); + int32_t mselect : bitfield(27, 27); + int32_t u1 : bitfield(28, 30); + int32_t pending : bitfield(31, 31); + } detail; + int32_t value; + } crt_fb_address; + +#define CRT_FB_WIDTH 0x080208 + /* CRT FB WIDTH + * Read/Write MMIO_base + 0x080208 + * Power-on Default Undefined + * + * 4:13 Number of 128-bit aligned bytes per line of the FB + * graphics plane + * 20:29 Number of bytes per line of the panel graphics window + * specified in 128-bit aligned bytes. + */ + union { + struct { + int32_t u0 : bitfield( 0, 3); + int32_t offset : bitfield( 4, 13); + int32_t u1 : bitfield(14, 19); + int32_t width : bitfield(20, 29); + } detail; + int32_t value; + } crt_fb_width; + +#define CRT_HTOTAL 0x08020c + /* CRT HORIZONTAL TOTAL + * Read/Write MMIO_base + 0x08020C + * Power-on Default Undefined + * + * 0:11 Crt horizontal display end specified as number of pixels - 1. + * 16:27 Crt horizontal total specified as number of pixels - 1. + */ + union { + struct { + int32_t end : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t total : bitfield(16, 27); + } detail; + int32_t value; + } crt_htotal; + +#define CRT_HSYNC 0x080210 + /* CRT HORIZONTAL SYNC + * Read/Write MMIO_base + 0x080210 + * Power-on Default Undefined + * + * 0:11 Crt horizontal sync start specified as pixel number - 1. + * 16:23 Crt horizontal sync width specified in pixels. + */ + union { + struct { + int32_t start : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t width : bitfield(16, 23); + } detail; + int32_t value; + } crt_hsync; + +#define CRT_VTOTAL 0x080214 + /* CRT VERTICAL TOTAL + * Read/Write MMIO_base + 0x080214 + * Power-on Default Undefined + * + * 0:10 Crt vertical display end specified as number of pixels - 1. + * 16:26 Crt vertical total specified as number of pixels - 1. + */ + union { + struct { + int32_t end : bitfield( 0, 10); + int32_t u0 : bitfield(11, 15); + int32_t total : bitfield(16, 26); + } detail; + int32_t value; + } crt_vtotal; + +#define CRT_VSYNC 0x080218 + /* CRT VERTICAL SYNC + * Read/Write MMIO_base + 0x080218 + * Power-on Default Undefined + * + * 0:11 Crt vertical sync start specified as pixel number - 1. + * 16:21 Crt vertical sync height specified in pixels. + */ + union { + struct { + int32_t start : bitfield( 0, 11); + int32_t u0 : bitfield(12, 15); + int32_t height : bitfield(16, 21); + } detail; + int32_t value; + } crt_vsync; +} MSOCRegRec, *MSOCRegPtr; -/****************************************************************************** - * D E F I N I T I O N S - ******************************************************************************/ - -/* Use PLL with 12MHz crystal instead of test clock. */ -#define USE_CRYSTAL_12 0 -/* Use PLL with 24MHz crystal instead of test clock. */ -#define USE_CRYSTAL_24 1 /* In Kb - documentation says it is 64Kb... */ #define FB_RESERVE4USB 512 -/* Power constants to use with SMI501_SetDPMS function. */ -typedef enum _DPMS_t { - DPMS_ON, - DPMS_STANDBY, - DPMS_SUSPEND, - DPMS_OFF -} DPMS_t; - -/* Display type constants to use with setMode function and others. */ -typedef enum _display_t { - PANEL, - CRT -} display_t; - -/* Type of LCD display */ -typedef enum _lcd_display_t { - LCD_TFT = 0, - LCD_STN_8 = 2, - LCD_STN_12 = 3 -} lcd_display_t; - -/* Polarity constants. */ -typedef enum _polarity_t { - POSITIVE, - NEGATIVE -} polarity_t; - -/* RGB color structure. */ -typedef struct { - unsigned char cBlue; - unsigned char cGreen; - unsigned char cRed; - unsigned char cFiller; -} RGB; - -/* Format of mode table record */ -typedef struct _mode_table_t { - /* Horizontal timing */ - int horizontal_total; - int horizontal_display_end; - int horizontal_sync_start; - int horizontal_sync_width; - polarity_t horizontal_sync_polarity; - - /* Vertical timing. */ - int vertical_total; - int vertical_display_end; - int vertical_sync_start; - int vertical_sync_height; - polarity_t vertical_sync_polarity; - - /* Refresh timing. */ - int pixel_clock; - int horizontal_frequency; - int vertical_frequency; -} mode_table_t, *pmode_table_t; - -/* Clock value structure. */ -typedef struct clock_select_t { - int mclk; - int divider; - int shift; -} clock_select_t, *pclock_select_t; - -/* Registers necessary to set mode. */ -typedef struct _reg_table_t { - unsigned int clock; - unsigned int control; - unsigned int fb_width; - unsigned int horizontal_total; - unsigned int horizontal_sync; - unsigned int vertical_total; - unsigned int vertical_sync; - unsigned int width; - unsigned int height; - display_t display; -} reg_table_t, *preg_table_t; - -/* Structure used to initialize CRT hardware module */ -typedef struct { - unsigned int mask; /* Holds flags indicating which register - * bitfields to init */ - unsigned int fifo_level; /* FIFO request level */ - unsigned int tvp; /* TV clock phase select */ - unsigned int cp; /* CRT clock phase select */ - unsigned int blank; /* CRT data blanking */ - unsigned int format; /* CRT graphics plane format */ -} init_crt, *pinit_crt; - -/* Structure used to initialize CRT cursor hardware module */ -typedef struct { - unsigned int mask; /* Holds flags indicating which register - * bitfields to init */ -} init_crt_hwc, *pinit_crt_hwc; - - -/* Panel On/Off constants to use with panelPowerSequence. */ -typedef enum _panel_state_t { - PANEL_OFF, - PANEL_ON -} panel_state_t; - -/******************************************************************************/ -/* M A C R O S */ -/******************************************************************************/ -/* Direct register access macro */ -#define REG_READ8(r) (*(volatile unsigned char *) &g_pRegisters[r]) -#define REG_READ16(r) (*(volatile unsighed short *)&g_pRegisters[r]) -#define REG_READ32(r) (*(volatile unsighed int *) &g_pRegisters[r]) -#define REG_WRITE8(r, v) \ - { *(volatile unsigned char *) &g_pRegisters[r] = (v); } -#define REG_WRITE16(r, v) \ - { *(volatile unsighed short *)&g_pRegisters[r] = (v); } -#define REG_WRITE32(r, v) \ - { *(volatile unsigned long *) &g_pRegisters[r] = (v); } - -/* Internal macros */ -#define _F_START(f) (0 ? f) -#define _F_END(f) (1 ? f) -#define _F_SIZE(f) (1 + _F_END(f) - _F_START(f)) -#define _F_MASK(f) (((1 << _F_SIZE(f)) - 1) << _F_START(f)) -#define _F_NORMALIZE(v, f) (((v) & _F_MASK(f)) >> _F_START(f)) -#define _F_DENORMALIZE(v, f) (((v) << _F_START(f)) & _F_MASK(f)) - -/* Global macros */ -#define FIELD_GET(x, reg, field) \ -( \ - _F_NORMALIZE((x), reg ## _ ## field) \ -) - -#define FIELD_SET(x, reg, field, value) \ -( \ - (x & ~_F_MASK(reg ## _ ## field)) | \ - _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \ -) - -#define FIELD_VALUE(x, reg, field, value) \ -( \ - (x & ~_F_MASK(reg ## _ ## field)) | \ - _F_DENORMALIZE(value, reg ## _ ## field) \ -) - -#define FIELD_CLEAR(reg, field) \ -( \ - ~ _F_MASK(reg ## _ ## field) \ -) - -/* Field Macros */ -#define FIELD_START(field) (0 ? field) -#define FIELD_END(field) (1 ? field) -#define FIELD_SIZE(field) \ - (1 + FIELD_END(field) - FIELD_START(field)) -#define FIELD_MASK(field) \ - (((1 << (FIELD_SIZE(field)-1)) | \ - ((1 << (FIELD_SIZE(field)-1)) - 1)) << FIELD_START(field)) -#define FIELD_NORMALIZE(reg, field) \ - (((reg) & FIELD_MASK(field)) >> FIELD_START(field)) -#define FIELD_DENORMALIZE(field, value) \ - (((value) << FIELD_START(field)) & FIELD_MASK(field)) - -#define FIELD_INIT(reg, field, value) \ - FIELD_DENORMALIZE(reg ## _ ## field, \ - reg ## _ ## field ## _ ## value) -#define FIELD_INIT_VAL(reg, field, value) \ - FIELD_DENORMALIZE(reg ## _ ## field, value) -#define FIELD_VAL_SET(x, r, f, v) x = x & ~FIELD_MASK(r ## _ ## f) - - -/****************************************************************************** - * F U N C T I O N P R O T O T Y P E S - ******************************************************************************/ -void SMI501_SetDPMS(SMIPtr pSmi, DPMS_t state); -Bool SMI501_SetMode(ScrnInfoPtr pScrn, DisplayModePtr mode); -unsigned int SMI501_Read32(SMIPtr pSmi, unsigned int nOffset); -void SMI501_Write32(SMIPtr pSmi, unsigned int nOffset, unsigned int nData); - -/* FIXME does something use it? */ -void DisableOverlay(SMIPtr pSmi); -void EnableOverlay(SMIPtr pSmi); - -/* TV clock phase select */ -#define DISP_CRT_TVP 0x00000100 -#define DISP_CRT_TVP_HIGH 0x00000000 -#define DISP_CRT_TVP_LOW 0x00008000 - -/* CRT clock phase select */ -#define DISP_CRT_CP 0x00000200 -#define DISP_CRT_CP_HIGH 0x00000000 -#define DISP_CRT_CP_LOW 0x00004000 - -/* CRT data blanking */ -#define DISP_CRT_BLANK 0x00000400 -#define DISP_CRT_BLANK_OFF 0x00000000 -#define DISP_CRT_BLANK_ON 0x00000400 - -/* CRT graphics plane format */ -#define DISP_CRT_FORMAT 0x00000800 -#define DISP_CRT_FORMAT_8 0x00000000 -#define DISP_CRT_FORMAT_16 0x00000001 -#define DISP_CRT_FORMAT_32 0x00000002 - -#define DISP_MODE_8_BPP 0 /* 8 bpp i8RGB */ -#define DISP_MODE_16_BPP 1 /* 16 bpp RGB565 */ -#define DISP_MODE_32_BPP 2 /* 32 bpp RGB888 */ -#define DISP_MODE_YUV 3 /* 16 bpp YUV422 */ -#define DISP_MODE_ALPHA_8 4 /* 8 bpp a4i4RGB */ -#define DISP_MODE_ALPHA_16 5 /* 16 bpp a4RGB444 */ - -#define DISP_PAN_LEFT 0 /* Pan left */ -#define DISP_PAN_RIGHT 1 /* Pan right */ -#define DISP_PAN_UP 2 /* Pan upwards */ -#define DISP_PAN_DOWN 3 /* Pan downwards */ - -#define DISP_DPMS_QUERY -1 /* Query DPMS value */ -#define DISP_DPMS_ON 0 /* DPMS on */ -#define DISP_DPMS_STANDBY 1 /* DPMS standby */ -#define DISP_DPMS_SUSPEND 2 /* DPMS suspend */ -#define DISP_DPMS_OFF 3 /* DPMS off */ - -#define DISP_DELAY_DEFAULT 0 /* Default delay */ - -/* Used in panelSetTiming, crtSetTiming if nHTotal, nVTotal not specified */ -#define DISP_HVTOTAL_UNKNOWN -1 -/* Used in panelSetTiming, crtSetTiming if nHTotal, nVTotal not specified */ -#define DISP_HVTOTAL_SCALEFACTOR 1.25 - -#define VGX_SIGNAL_PANEL_VSYNC 100 /* Panel VSYNC */ -#define VGX_SIGNAL_PANEL_PAN 101 /* auto panning complete*/ -#define VGX_SIGNAL_CRT_VSYNC 102 /* CRT VSYNC */ - -#define VSYNCTIMEOUT 10000 - -/* Use per-pixel alpha values */ -#define ALPHA_MODE_PER_PIXEL 0 -/* Use alpha value specified in Alpha bitfield */ -#define ALPHA_MODE_ALPHA 1 -/* Number of colors in alpha/video alpha palette */ -#define ALPHA_COLOR_LUT_SIZE 16 - -/* Cursor is within screen top/left boundary */ -#define HWC_ON_SCREEN 0 -/* Cursor is outside screen top/left boundary */ -#define HWC_OFF_SCREEN 1 -/* Number of cursor colors */ -#define HWC_NUM_COLORS 3 - -#define RGB565_R_MASK 0xF8 /* Mask for red color */ -#define RGB565_G_MASK 0xFC /* Mask for green color */ -#define RGB565_B_MASK 0xF8 /* Mask for blue color */ - -/* Number of bits to shift for red color */ -#define RGB565_R_SHIFT 8 -/* Number of bits to shift for green color */ -#define RGB565_G_SHIFT 3 -/* Number of bits to shift for blue color */ -#define RGB565_B_SHIFT 3 - -#define RGB16(r, g, b) \ -( \ - (unsigned short)((((r) & RGB565_R_MASK) << RGB565_R_SHIFT) | \ - (((g) & RGB565_G_MASK) << RGB565_G_SHIFT) | \ - (((b) & RGB565_B_MASK) >> RGB565_B_SHIFT)) \ -) - -/* REGISTER DEFINITIONS */ - -/* regSC.h */ -#define SYSTEM_CTRL 0x000000 -#define SYSTEM_CTRL_DPMS 31:30 -#define SYSTEM_CTRL_DPMS_VPHP 0 -#define SYSTEM_CTRL_DPMS_VPHN 1 -#define SYSTEM_CTRL_DPMS_VNHP 2 -#define SYSTEM_CTRL_DPMS_VNHN 3 -#define SYSTEM_CTRL_PCI_BURST 29:29 -#define SYSTEM_CTRL_PCI_BURST_DISABLE 0 -#define SYSTEM_CTRL_PCI_BURST_ENABLE 1 -#define SYSTEM_CTRL_CSC_STATUS 28:28 -#define SYSTEM_CTRL_CSC_STATUS_IDLE 0 -#define SYSTEM_CTRL_CSC_STATUS_BUSY 1 -#define SYSTEM_CTRL_PCI_MASTER 25:25 -#define SYSTEM_CTRL_PCI_MASTER_STOP 0 -#define SYSTEM_CTRL_PCI_MASTER_START 1 -#define SYSTEM_CTRL_LATENCY_TIMER 24:24 -#define SYSTEM_CTRL_LATENCY_TIMER_ENABLE 0 -#define SYSTEM_CTRL_LATENCY_TIMER_DISABLE 1 -#define SYSTEM_CTRL_PANEL_STATUS 23:23 -#define SYSTEM_CTRL_PANEL_STATUS_CURRENT 0 -#define SYSTEM_CTRL_PANEL_STATUS_PENDING 1 -#define SYSTEM_CTRL_VIDEO_STATUS 22:22 -#define SYSTEM_CTRL_VIDEO_STATUS_CURRENT 0 -#define SYSTEM_CTRL_VIDEO_STATUS_PENDING 1 -#define SYSTEM_CTRL_DE_FIFO 20:20 -#define SYSTEM_CTRL_DE_FIFO_NOT_EMPTY 0 -#define SYSTEM_CTRL_DE_FIFO_EMPTY 1 -#define SYSTEM_CTRL_DE_STATUS 19:19 -#define SYSTEM_CTRL_DE_STATUS_IDLE 0 -#define SYSTEM_CTRL_DE_STATUS_BUSY 1 -#define SYSTEM_CTRL_CRT_STATUS 17:17 -#define SYSTEM_CTRL_CRT_STATUS_CURRENT 0 -#define SYSTEM_CTRL_CRT_STATUS_PENDING 1 -#define SYSTEM_CTRL_ZVPORT 16:16 -#define SYSTEM_CTRL_ZVPORT_0 0 -#define SYSTEM_CTRL_ZVPORT_1 1 -#define SYSTEM_CTRL_PCI_BURST_READ 15:15 -#define SYSTEM_CTRL_PCI_BURST_READ_DISABLE 0 -#define SYSTEM_CTRL_PCI_BURST_READ_ENABLE 1 -#define SYSTEM_CTRL_DE_ABORT 13:12 -#define SYSTEM_CTRL_DE_ABORT_NORMAL 0 -#define SYSTEM_CTRL_DE_ABORT_2D_ABORT 3 -#define SYSTEM_CTRL_PCI_SUBSYS_LOCK 11:11 -#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_DISABLE 0 -#define SYSTEM_CTRL_PCI_SUBSYS_LOCK_ENABLE 1 -#define SYSTEM_CTRL_PCI_RETRY 7:7 -#define SYSTEM_CTRL_PCI_RETRY_ENABLE 0 -#define SYSTEM_CTRL_PCI_RETRY_DISABLE 1 -#define SYSTEM_CTRL_PCI_CLOCK_RUN 6:6 -#define SYSTEM_CTRL_PCI_CLOCK_RUN_DISABLE 0 -#define SYSTEM_CTRL_PCI_CLOCK_RUN_ENABLE 1 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE 5:4 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 0 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 1 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 2 -#define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 3 -#define SYSTEM_CTRL_CRT_TRISTATE 2:2 -#define SYSTEM_CTRL_CRT_TRISTATE_DISABLE 0 -#define SYSTEM_CTRL_CRT_TRISTATE_ENABLE 1 -#define SYSTEM_CTRL_INTMEM_TRISTATE 1:1 -#define SYSTEM_CTRL_INTMEM_TRISTATE_DISABLE 0 -#define SYSTEM_CTRL_INTMEM_TRISTATE_ENABLE 1 -#define SYSTEM_CTRL_PANEL_TRISTATE 0:0 -#define SYSTEM_CTRL_PANEL_TRISTATE_DISABLE 0 -#define SYSTEM_CTRL_PANEL_TRISTATE_ENABLE 1 - -#define DRAM_CTRL 0x000010 -#define DRAM_CTRL_EMBEDDED 31:31 -#define DRAM_CTRL_EMBEDDED_ENABLE 0 -#define DRAM_CTRL_EMBEDDED_DISABLE 1 -#define DRAM_CTRL_CPU_BURST 30:28 -#define DRAM_CTRL_CPU_BURST_1 0 -#define DRAM_CTRL_CPU_BURST_2 1 -#define DRAM_CTRL_CPU_BURST_4 2 -#define DRAM_CTRL_CPU_BURST_8 3 -#define DRAM_CTRL_CPU_CAS_LATENCY 27:27 -#define DRAM_CTRL_CPU_CAS_LATENCY_2 0 -#define DRAM_CTRL_CPU_CAS_LATENCY_3 1 -#define DRAM_CTRL_CPU_SIZE 26:24 -#define DRAM_CTRL_CPU_SIZE_2 0 -#define DRAM_CTRL_CPU_SIZE_4 1 -#define DRAM_CTRL_CPU_SIZE_64 4 -#define DRAM_CTRL_CPU_SIZE_32 5 -#define DRAM_CTRL_CPU_SIZE_16 6 -#define DRAM_CTRL_CPU_SIZE_8 7 -#define DRAM_CTRL_CPU_COLUMN_SIZE 23:22 -#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 0 -#define DRAM_CTRL_CPU_COLUMN_SIZE_512 2 -#define DRAM_CTRL_CPU_COLUMN_SIZE_256 3 -#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE 21:21 -#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE_6 0 -#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE_7 1 -#define DRAM_CTRL_CPU_RESET 20:20 -#define DRAM_CTRL_CPU_RESET_ENABLE 0 -#define DRAM_CTRL_CPU_RESET_DISABLE 1 -#define DRAM_CTRL_CPU_BANKS 19:19 -#define DRAM_CTRL_CPU_BANKS_2 0 -#define DRAM_CTRL_CPU_BANKS_4 1 -#define DRAM_CTRL_CPU_WRITE_PRECHARGE 18:18 -#define DRAM_CTRL_CPU_WRITE_PRECHARGE_2 0 -#define DRAM_CTRL_CPU_WRITE_PRECHARGE_1 1 -#define DRAM_CTRL_BLOCK_WRITE 17:17 -#define DRAM_CTRL_BLOCK_WRITE_DISABLE 0 -#define DRAM_CTRL_BLOCK_WRITE_ENABLE 1 -#define DRAM_CTRL_REFRESH_COMMAND 16:16 -#define DRAM_CTRL_REFRESH_COMMAND_10 0 -#define DRAM_CTRL_REFRESH_COMMAND_12 1 -#define DRAM_CTRL_SIZE 15:13 -#define DRAM_CTRL_SIZE_4 0 -#define DRAM_CTRL_SIZE_8 1 -#define DRAM_CTRL_SIZE_16 2 -#define DRAM_CTRL_SIZE_32 3 -#define DRAM_CTRL_SIZE_64 4 -#define DRAM_CTRL_SIZE_2 5 -#define DRAM_CTRL_COLUMN_SIZE 12:11 -#define DRAM_CTRL_COLUMN_SIZE_256 0 -#define DRAM_CTRL_COLUMN_SIZE_512 2 -#define DRAM_CTRL_COLUMN_SIZE_1024 3 -#define DRAM_CTRL_BLOCK_WRITE_TIME 10:10 -#define DRAM_CTRL_BLOCK_WRITE_TIME_1 0 -#define DRAM_CTRL_BLOCK_WRITE_TIME_2 1 -#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE 9:9 -#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE_4 0 -#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE_1 1 -#define DRAM_CTRL_ACTIVE_PRECHARGE 8:8 -#define DRAM_CTRL_ACTIVE_PRECHARGE_6 0 -#define DRAM_CTRL_ACTIVE_PRECHARGE_7 1 -#define DRAM_CTRL_RESET 7:7 -#define DRAM_CTRL_RESET_ENABLE 0 -#define DRAM_CTRL_RESET_DISABLE 1 -#define DRAM_CTRL_REMAIN_ACTIVE 6:6 -#define DRAM_CTRL_REMAIN_ACTIVE_ENABLE 0 -#define DRAM_CTRL_REMAIN_ACTIVE_DISABLE 1 -#define DRAM_CTRL_BANKS 1:1 -#define DRAM_CTRL_BANKS_2 1 -#define DRAM_CTRL_BANKS_4 0 -#define DRAM_CTRL_WRITE_PRECHARGE 0:0 -#define DRAM_CTRL_WRITE_PRECHARGE_2 0 -#define DRAM_CTRL_WRITE_PRECHARGE_1 1 - -#define CURRENT_POWER_CLOCK 0x00003C -#define CURRENT_POWER_CLOCK_P2XCLK_SELECT 29:29 -#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER 28:27 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5 2 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT 26:24 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7 7 -#define CURRENT_POWER_CLOCK_V2XCLK_SELECT 20:20 -#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER 19:19 -#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT 18:16 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7 7 -#define CURRENT_POWER_CLOCK_MCLK_SELECT 12:12 -#define CURRENT_POWER_CLOCK_MCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_MCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_MCLK_DIVIDER 11:11 -#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT 10:8 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7 7 -#define CURRENT_POWER_CLOCK_M2XCLK_SELECT 4:4 -#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER 3:3 -#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT 2:0 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7 7 - -#define CURRENT_POWER_GATE 0x000038 -#define CURRENT_POWER_GATE_AC97_I2S 18:18 -#define CURRENT_POWER_GATE_AC97_I2S_DISABLE 0 -#define CURRENT_POWER_GATE_AC97_I2S_ENABLE 1 -#define CURRENT_POWER_GATE_8051 17:17 -#define CURRENT_POWER_GATE_8051_DISABLE 0 -#define CURRENT_POWER_GATE_8051_ENABLE 1 -#define CURRENT_POWER_GATE_PLL 16:16 -#define CURRENT_POWER_GATE_PLL_DISABLE 0 -#define CURRENT_POWER_GATE_PLL_ENABLE 1 -#define CURRENT_POWER_GATE_OSCILLATOR 15:15 -#define CURRENT_POWER_GATE_OSCILLATOR_DISABLE 0 -#define CURRENT_POWER_GATE_OSCILLATOR_ENABLE 1 -#define CURRENT_POWER_GATE_PLL_RECOVERY 14:13 -#define CURRENT_POWER_GATE_PLL_RECOVERY_32 0 -#define CURRENT_POWER_GATE_PLL_RECOVERY_64 1 -#define CURRENT_POWER_GATE_PLL_RECOVERY_96 2 -#define CURRENT_POWER_GATE_PLL_RECOVERY_128 3 -#define CURRENT_POWER_GATE_USB_SLAVE 12:12 -#define CURRENT_POWER_GATE_USB_SLAVE_DISABLE 0 -#define CURRENT_POWER_GATE_USB_SLAVE_ENABLE 1 -#define CURRENT_POWER_GATE_USB_HOST 11:11 -#define CURRENT_POWER_GATE_USB_HOST_DISABLE 0 -#define CURRENT_POWER_GATE_USB_HOST_ENABLE 1 -#define CURRENT_POWER_GATE_SSP0_SSP1 10:10 -#define CURRENT_POWER_GATE_SSP0_SSP1_DISABLE 0 -#define CURRENT_POWER_GATE_SSP0_SSP1_ENABLE 1 -#define CURRENT_POWER_GATE_UART1 8:8 -#define CURRENT_POWER_GATE_UART1_DISABLE 0 -#define CURRENT_POWER_GATE_UART1_ENABLE 1 -#define CURRENT_POWER_GATE_UART0 7:7 -#define CURRENT_POWER_GATE_UART0_DISABLE 0 -#define CURRENT_POWER_GATE_UART0_ENABLE 1 -#define CURRENT_POWER_GATE_GPIO_PWM_I2C 6:6 -#define CURRENT_POWER_GATE_GPIO_PWM_I2C_DISABLE 0 -#define CURRENT_POWER_GATE_GPIO_PWM_I2C_ENABLE 1 -#define CURRENT_POWER_GATE_ZVPORT 5:5 -#define CURRENT_POWER_GATE_ZVPORT_DISABLE 0 -#define CURRENT_POWER_GATE_ZVPORT_ENABLE 1 -#define CURRENT_POWER_GATE_CSC 4:4 -#define CURRENT_POWER_GATE_CSC_DISABLE 0 -#define CURRENT_POWER_GATE_CSC_ENABLE 1 -#define CURRENT_POWER_GATE_2D 3:3 -#define CURRENT_POWER_GATE_2D_DISABLE 0 -#define CURRENT_POWER_GATE_2D_ENABLE 1 -#define CURRENT_POWER_GATE_DISPLAY 2:2 -#define CURRENT_POWER_GATE_DISPLAY_DISABLE 0 -#define CURRENT_POWER_GATE_DISPLAY_ENABLE 1 -#define CURRENT_POWER_GATE_INTMEM 1:1 -#define CURRENT_POWER_GATE_INTMEM_DISABLE 0 -#define CURRENT_POWER_GATE_INTMEM_ENABLE 1 -#define CURRENT_POWER_GATE_HOST 0:0 -#define CURRENT_POWER_GATE_HOST_DISABLE 0 -#define CURRENT_POWER_GATE_HOST_ENABLE 1 - -#define CURRENT_POWER_CLOCK 0x00003C -#define CURRENT_POWER_CLOCK_P2XCLK_SELECT 29:29 -#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_P2XCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER 28:27 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_P2XCLK_DIVIDER_5 2 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT 26:24 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_P2XCLK_SHIFT_7 7 -#define CURRENT_POWER_CLOCK_V2XCLK_SELECT 20:20 -#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_V2XCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER 19:19 -#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_V2XCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT 18:16 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_V2XCLK_SHIFT_7 7 -#define CURRENT_POWER_CLOCK_MCLK_SELECT 12:12 -#define CURRENT_POWER_CLOCK_MCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_MCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_MCLK_DIVIDER 11:11 -#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_MCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT 10:8 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_MCLK_SHIFT_7 7 -#define CURRENT_POWER_CLOCK_M2XCLK_SELECT 4:4 -#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_288 0 -#define CURRENT_POWER_CLOCK_M2XCLK_SELECT_336 1 -#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER 3:3 -#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_1 0 -#define CURRENT_POWER_CLOCK_M2XCLK_DIVIDER_3 1 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT 2:0 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_0 0 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_1 1 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_2 2 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_3 3 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_4 4 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_5 5 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_6 6 -#define CURRENT_POWER_CLOCK_M2XCLK_SHIFT_7 7 - -#define POWER_MODE0_GATE 0x000040 -#define POWER_MODE0_GATE_AC97_I2S 18:18 -#define POWER_MODE0_GATE_AC97_I2S_DISABLE 0 -#define POWER_MODE0_GATE_AC97_I2S_ENABLE 1 -#define POWER_MODE0_GATE_8051 17:17 -#define POWER_MODE0_GATE_8051_DISABLE 0 -#define POWER_MODE0_GATE_8051_ENABLE 1 -#define POWER_MODE0_GATE_USB_SLAVE 12:12 -#define POWER_MODE0_GATE_USB_SLAVE_DISABLE 0 -#define POWER_MODE0_GATE_USB_SLAVE_ENABLE 1 -#define POWER_MODE0_GATE_USB_HOST 11:11 -#define POWER_MODE0_GATE_USB_HOST_DISABLE 0 -#define POWER_MODE0_GATE_USB_HOST_ENABLE 1 -#define POWER_MODE0_GATE_SSP0_SSP1 10:10 -#define POWER_MODE0_GATE_SSP0_SSP1_DISABLE 0 -#define POWER_MODE0_GATE_SSP0_SSP1_ENABLE 1 -#define POWER_MODE0_GATE_UART1 8:8 -#define POWER_MODE0_GATE_UART1_DISABLE 0 -#define POWER_MODE0_GATE_UART1_ENABLE 1 -#define POWER_MODE0_GATE_UART0 7:7 -#define POWER_MODE0_GATE_UART0_DISABLE 0 -#define POWER_MODE0_GATE_UART0_ENABLE 1 -#define POWER_MODE0_GATE_GPIO_PWM_I2C 6:6 -#define POWER_MODE0_GATE_GPIO_PWM_I2C_DISABLE 0 -#define POWER_MODE0_GATE_GPIO_PWM_I2C_ENABLE 1 -#define POWER_MODE0_GATE_ZVPORT 5:5 -#define POWER_MODE0_GATE_ZVPORT_DISABLE 0 -#define POWER_MODE0_GATE_ZVPORT_ENABLE 1 -#define POWER_MODE0_GATE_CSC 4:4 -#define POWER_MODE0_GATE_CSC_DISABLE 0 -#define POWER_MODE0_GATE_CSC_ENABLE 1 -#define POWER_MODE0_GATE_2D 3:3 -#define POWER_MODE0_GATE_2D_DISABLE 0 -#define POWER_MODE0_GATE_2D_ENABLE 1 -#define POWER_MODE0_GATE_DISPLAY 2:2 -#define POWER_MODE0_GATE_DISPLAY_DISABLE 0 -#define POWER_MODE0_GATE_DISPLAY_ENABLE 1 -#define POWER_MODE0_GATE_INTMEM 1:1 -#define POWER_MODE0_GATE_INTMEM_DISABLE 0 -#define POWER_MODE0_GATE_INTMEM_ENABLE 1 -#define POWER_MODE0_GATE_HOST 0:0 -#define POWER_MODE0_GATE_HOST_DISABLE 0 -#define POWER_MODE0_GATE_HOST_ENABLE 1 - -#define POWER_MODE0_CLOCK 0x000044 -#define POWER_MODE0_CLOCK_P2XCLK_SELECT 29:29 -#define POWER_MODE0_CLOCK_P2XCLK_SELECT_288 0 -#define POWER_MODE0_CLOCK_P2XCLK_SELECT_336 1 -#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER 28:27 -#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_1 0 -#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_3 1 -#define POWER_MODE0_CLOCK_P2XCLK_DIVIDER_5 2 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT 26:24 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_0 0 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_1 1 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_2 2 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_3 3 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_4 4 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_5 5 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_6 6 -#define POWER_MODE0_CLOCK_P2XCLK_SHIFT_7 7 -#define POWER_MODE0_CLOCK_V2XCLK_SELECT 20:20 -#define POWER_MODE0_CLOCK_V2XCLK_SELECT_288 0 -#define POWER_MODE0_CLOCK_V2XCLK_SELECT_336 1 -#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER 19:19 -#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_1 0 -#define POWER_MODE0_CLOCK_V2XCLK_DIVIDER_3 1 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT 18:16 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_0 0 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_1 1 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_2 2 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_3 3 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_4 4 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_5 5 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_6 6 -#define POWER_MODE0_CLOCK_V2XCLK_SHIFT_7 7 -#define POWER_MODE0_CLOCK_MCLK_SELECT 12:12 -#define POWER_MODE0_CLOCK_MCLK_SELECT_288 0 -#define POWER_MODE0_CLOCK_MCLK_SELECT_336 1 -#define POWER_MODE0_CLOCK_MCLK_DIVIDER 11:11 -#define POWER_MODE0_CLOCK_MCLK_DIVIDER_1 0 -#define POWER_MODE0_CLOCK_MCLK_DIVIDER_3 1 -#define POWER_MODE0_CLOCK_MCLK_SHIFT 10:8 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_0 0 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_1 1 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_2 2 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_3 3 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_4 4 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_5 5 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_6 6 -#define POWER_MODE0_CLOCK_MCLK_SHIFT_7 7 -#define POWER_MODE0_CLOCK_M2XCLK_SELECT 4:4 -#define POWER_MODE0_CLOCK_M2XCLK_SELECT_288 0 -#define POWER_MODE0_CLOCK_M2XCLK_SELECT_336 1 -#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER 3:3 -#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_1 0 -#define POWER_MODE0_CLOCK_M2XCLK_DIVIDER_3 1 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT 2:0 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_0 0 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_1 1 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_2 2 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_3 3 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_4 4 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_5 5 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_6 6 -#define POWER_MODE0_CLOCK_M2XCLK_SHIFT_7 7 - -#define POWER_MODE1_GATE 0x000048 -#define POWER_MODE1_GATE_AC97_I2S 18:18 -#define POWER_MODE1_GATE_AC97_I2S_DISABLE 0 -#define POWER_MODE1_GATE_AC97_I2S_ENABLE 1 -#define POWER_MODE1_GATE_8051 17:17 -#define POWER_MODE1_GATE_8051_DISABLE 0 -#define POWER_MODE1_GATE_8051_ENABLE 1 -#define POWER_MODE1_GATE_USB_SLAVE 12:12 -#define POWER_MODE1_GATE_USB_SLAVE_DISABLE 0 -#define POWER_MODE1_GATE_USB_SLAVE_ENABLE 1 -#define POWER_MODE1_GATE_USB_HOST 11:11 -#define POWER_MODE1_GATE_USB_HOST_DISABLE 0 -#define POWER_MODE1_GATE_USB_HOST_ENABLE 1 -#define POWER_MODE1_GATE_SSP0_SSP1 10:10 -#define POWER_MODE1_GATE_SSP0_SSP1_DISABLE 0 -#define POWER_MODE1_GATE_SSP0_SSP1_ENABLE 1 -#define POWER_MODE1_GATE_UART1 8:8 -#define POWER_MODE1_GATE_UART1_DISABLE 0 -#define POWER_MODE1_GATE_UART1_ENABLE 1 -#define POWER_MODE1_GATE_UART0 7:7 -#define POWER_MODE1_GATE_UART0_DISABLE 0 -#define POWER_MODE1_GATE_UART0_ENABLE 1 -#define POWER_MODE1_GATE_GPIO_PWM_I2C 6:6 -#define POWER_MODE1_GATE_GPIO_PWM_I2C_DISABLE 0 -#define POWER_MODE1_GATE_GPIO_PWM_I2C_ENABLE 1 -#define POWER_MODE1_GATE_ZVPORT 5:5 -#define POWER_MODE1_GATE_ZVPORT_DISABLE 0 -#define POWER_MODE1_GATE_ZVPORT_ENABLE 1 -#define POWER_MODE1_GATE_CSC 4:4 -#define POWER_MODE1_GATE_CSC_DISABLE 0 -#define POWER_MODE1_GATE_CSC_ENABLE 1 -#define POWER_MODE1_GATE_2D 3:3 -#define POWER_MODE1_GATE_2D_DISABLE 0 -#define POWER_MODE1_GATE_2D_ENABLE 1 -#define POWER_MODE1_GATE_DISPLAY 2:2 -#define POWER_MODE1_GATE_DISPLAY_DISABLE 0 -#define POWER_MODE1_GATE_DISPLAY_ENABLE 1 -#define POWER_MODE1_GATE_INTMEM 1:1 -#define POWER_MODE1_GATE_INTMEM_DISABLE 0 -#define POWER_MODE1_GATE_INTMEM_ENABLE 1 -#define POWER_MODE1_GATE_HOST 0:0 -#define POWER_MODE1_GATE_HOST_DISABLE 0 -#define POWER_MODE1_GATE_HOST_ENABLE 1 - -#define POWER_MODE1_CLOCK 0x00004C -#define POWER_MODE1_CLOCK_P2XCLK_SELECT 29:29 -#define POWER_MODE1_CLOCK_P2XCLK_SELECT_288 0 -#define POWER_MODE1_CLOCK_P2XCLK_SELECT_336 1 -#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER 28:27 -#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_1 0 -#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_3 1 -#define POWER_MODE1_CLOCK_P2XCLK_DIVIDER_5 2 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT 26:24 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_0 0 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_1 1 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_2 2 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_3 3 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_4 4 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_5 5 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_6 6 -#define POWER_MODE1_CLOCK_P2XCLK_SHIFT_7 7 -#define POWER_MODE1_CLOCK_V2XCLK_SELECT 20:20 -#define POWER_MODE1_CLOCK_V2XCLK_SELECT_288 0 -#define POWER_MODE1_CLOCK_V2XCLK_SELECT_336 1 -#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER 19:19 -#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_1 0 -#define POWER_MODE1_CLOCK_V2XCLK_DIVIDER_3 1 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT 18:16 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_0 0 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_1 1 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_2 2 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_3 3 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_4 4 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_5 5 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_6 6 -#define POWER_MODE1_CLOCK_V2XCLK_SHIFT_7 7 -#define POWER_MODE1_CLOCK_MCLK_SELECT 12:12 -#define POWER_MODE1_CLOCK_MCLK_SELECT_288 0 -#define POWER_MODE1_CLOCK_MCLK_SELECT_336 1 -#define POWER_MODE1_CLOCK_MCLK_DIVIDER 11:11 -#define POWER_MODE1_CLOCK_MCLK_DIVIDER_1 0 -#define POWER_MODE1_CLOCK_MCLK_DIVIDER_3 1 -#define POWER_MODE1_CLOCK_MCLK_SHIFT 10:8 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_0 0 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_1 1 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_2 2 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_3 3 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_4 4 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_5 5 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_6 6 -#define POWER_MODE1_CLOCK_MCLK_SHIFT_7 7 -#define POWER_MODE1_CLOCK_M2XCLK_SELECT 4:4 -#define POWER_MODE1_CLOCK_M2XCLK_SELECT_288 0 -#define POWER_MODE1_CLOCK_M2XCLK_SELECT_336 1 -#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER 3:3 -#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_1 0 -#define POWER_MODE1_CLOCK_M2XCLK_DIVIDER_3 1 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT 2:0 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_0 0 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_1 1 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_2 2 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_3 3 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_4 4 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_5 5 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_6 6 -#define POWER_MODE1_CLOCK_M2XCLK_SHIFT_7 7 - -#define POWER_SLEEP_GATE 0x000050 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK 22:19 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_4096 0 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_2048 1 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_1024 2 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_512 3 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_256 4 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_128 5 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_64 6 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_32 7 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_16 8 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_8 9 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_4 10 -#define POWER_SLEEP_GATE_PLL_RECOVERY_CLOCK_2 11 -#define POWER_SLEEP_GATE_PLL_RECOVERY 14:13 -#define POWER_SLEEP_GATE_PLL_RECOVERY_32 0 -#define POWER_SLEEP_GATE_PLL_RECOVERY_64 1 -#define POWER_SLEEP_GATE_PLL_RECOVERY_96 2 -#define POWER_SLEEP_GATE_PLL_RECOVERY_128 3 - -#define POWER_MODE_CTRL 0x000054 -#define POWER_MODE_CTRL_SLEEP_STATUS 2:2 -#define POWER_MODE_CTRL_SLEEP_STATUS_INACTIVE 0 -#define POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE 1 -#define POWER_MODE_CTRL_MODE 1:0 -#define POWER_MODE_CTRL_MODE_MODE0 0 -#define POWER_MODE_CTRL_MODE_MODE1 1 -#define POWER_MODE_CTRL_MODE_SLEEP 2 - -#define MISC_CTRL 0x000004 -#define MISC_CTRL_PCI_PAD 31:30 -#define MISC_CTRL_PCI_PAD_24MA 0 -#define MISC_CTRL_PCI_PAD_12MA 1 -#define MISC_CTRL_PCI_PAD_8MA 2 -#define MISC_CTRL_48_SELECT 29:28 -#define MISC_CTRL_48_SELECT_CRYSTAL 0 -#define MISC_CTRL_48_SELECT_CPU_96 2 -#define MISC_CTRL_48_SELECT_CPU_48 3 -#define MISC_CTRL_UART1_SELECT 27:27 -#define MISC_CTRL_UART1_SELECT_UART 0 -#define MISC_CTRL_UART1_SELECT_SSP 1 -#define MISC_CTRL_8051_LATCH 26:26 -#define MISC_CTRL_8051_LATCH_DISABLE 0 -#define MISC_CTRL_8051_LATCH_ENABLE 1 -#define MISC_CTRL_FPDATA 25:25 -#define MISC_CTRL_FPDATA_18 0 -#define MISC_CTRL_FPDATA_24 1 -#define MISC_CTRL_CRYSTAL 24:24 -#define MISC_CTRL_CRYSTAL_24 0 -#define MISC_CTRL_CRYSTAL_12 1 -#define MISC_CTRL_DRAM_REFRESH 22:21 -#define MISC_CTRL_DRAM_REFRESH_8 0 -#define MISC_CTRL_DRAM_REFRESH_16 1 -#define MISC_CTRL_DRAM_REFRESH_32 2 -#define MISC_CTRL_DRAM_REFRESH_64 3 -#define MISC_CTRL_BUS_HOLD 20:18 -#define MISC_CTRL_BUS_HOLD_FIFO_EMPTY 0 -#define MISC_CTRL_BUS_HOLD_8 1 -#define MISC_CTRL_BUS_HOLD_16 2 -#define MISC_CTRL_BUS_HOLD_24 3 -#define MISC_CTRL_BUS_HOLD_32 4 -#define MISC_CTRL_HITACHI_READY 17:17 -#define MISC_CTRL_HITACHI_READY_NEGATIVE 0 -#define MISC_CTRL_HITACHI_READY_POSITIVE 1 -#define MISC_CTRL_INTERRUPT 16:16 -#define MISC_CTRL_INTERRUPT_NORMAL 0 -#define MISC_CTRL_INTERRUPT_INVERT 1 -#define MISC_CTRL_PLL_CLOCK_COUNT 15:15 -#define MISC_CTRL_PLL_CLOCK_COUNT_DISABLE 0 -#define MISC_CTRL_PLL_CLOCK_COUNT_ENABLE 1 -#define MISC_CTRL_DAC_BAND_GAP 14:13 -#define MISC_CTRL_DAC_POWER 12:12 -#define MISC_CTRL_DAC_POWER_ENABLE 0 -#define MISC_CTRL_DAC_POWER_DISABLE 1 -#define MISC_CTRL_USB_SLAVE_CONTROLLER 11:11 -#define MISC_CTRL_USB_SLAVE_CONTROLLER_CPU 0 -#define MISC_CTRL_USB_SLAVE_CONTROLLER_8051 1 -#define MISC_CTRL_BURST_LENGTH 10:10 -#define MISC_CTRL_BURST_LENGTH_8 0 -#define MISC_CTRL_BURST_LENGTH_1 1 -#define MISC_CTRL_USB_SELECT 9:9 -#define MISC_CTRL_USB_SELECT_MASTER 0 -#define MISC_CTRL_USB_SELECT_SLAVE 1 -#define MISC_CTRL_LOOPBACK 8:8 -#define MISC_CTRL_LOOPBACK_NORMAL 0 -#define MISC_CTRL_LOOPBACK_USB_HOST 1 -#define MISC_CTRL_CLOCK_DIVIDER_RESET 7:7 -#define MISC_CTRL_CLOCK_DIVIDER_RESET_ENABLE 0 -#define MISC_CTRL_CLOCK_DIVIDER_RESET_DISABLE 1 -#define MISC_CTRL_TEST_MODE 6:5 -#define MISC_CTRL_TEST_MODE_NORMAL 0 -#define MISC_CTRL_TEST_MODE_DEBUGGING 1 -#define MISC_CTRL_TEST_MODE_NAND 2 -#define MISC_CTRL_TEST_MODE_MEMORY 3 -#define MISC_CTRL_NEC_MMIO 4:4 -#define MISC_CTRL_NEC_MMIO_30 0 -#define MISC_CTRL_NEC_MMIO_62 1 -#define MISC_CTRL_CLOCK 3:3 -#define MISC_CTRL_CLOCK_PLL 0 -#define MISC_CTRL_CLOCK_TEST 1 -#define MISC_CTRL_HOST_BUS 2:0 -#define MISC_CTRL_HOST_BUS_HITACHI 0 -#define MISC_CTRL_HOST_BUS_PCI 1 -#define MISC_CTRL_HOST_BUS_XSCALE 2 -#define MISC_CTRL_HOST_BUS_STRONGARM 4 -#define MISC_CTRL_HOST_BUS_NEC 6 - -#define CMD_INTPR_STATUS 0x000024 -#define CMD_INTPR_STATUS_2D_MEMORY_FIFO 20:20 -#define CMD_INTPR_STATUS_2D_MEMORY_FIFO_NOT_EMPTY 0 -#define CMD_INTPR_STATUS_2D_MEMORY_FIFO_EMPTY 1 -#define CMD_INTPR_STATUS_COMMAND_FIFO 19:19 -#define CMD_INTPR_STATUS_COMMAND_FIFO_NOT_EMPTY 0 -#define CMD_INTPR_STATUS_COMMAND_FIFO_EMPTY 1 -#define CMD_INTPR_STATUS_CSC_STATUS 18:18 -#define CMD_INTPR_STATUS_CSC_STATUS_IDLE 0 -#define CMD_INTPR_STATUS_CSC_STATUS_BUSY 1 -#define CMD_INTPR_STATUS_MEMORY_DMA 17:17 -#define CMD_INTPR_STATUS_MEMORY_DMA_IDLE 0 -#define CMD_INTPR_STATUS_MEMORY_DMA_BUSY 1 -#define CMD_INTPR_STATUS_CRT_STATUS 16:16 -#define CMD_INTPR_STATUS_CRT_STATUS_CURRENT 0 -#define CMD_INTPR_STATUS_CRT_STATUS_PENDING 1 -#define CMD_INTPR_STATUS_CURRENT_FIELD 15:15 -#define CMD_INTPR_STATUS_CURRENT_FIELD_ODD 0 -#define CMD_INTPR_STATUS_CURRENT_FIELD_EVEN 1 -#define CMD_INTPR_STATUS_VIDEO_STATUS 14:14 -#define CMD_INTPR_STATUS_VIDEO_STATUS_CURRENT 0 -#define CMD_INTPR_STATUS_VIDEO_STATUS_PENDING 1 -#define CMD_INTPR_STATUS_PANEL_STATUS 13:13 -#define CMD_INTPR_STATUS_PANEL_STATUS_CURRENT 0 -#define CMD_INTPR_STATUS_PANEL_STATUS_PENDING 1 -#define CMD_INTPR_STATUS_CRT_SYNC 12:12 -#define CMD_INTPR_STATUS_CRT_SYNC_INACTIVE 0 -#define CMD_INTPR_STATUS_CRT_SYNC_ACTIVE 1 -#define CMD_INTPR_STATUS_PANEL_SYNC 11:11 -#define CMD_INTPR_STATUS_PANEL_SYNC_INACTIVE 0 -#define CMD_INTPR_STATUS_PANEL_SYNC_ACTIVE 1 -#define CMD_INTPR_STATUS_2D_SETUP 2:2 -#define CMD_INTPR_STATUS_2D_SETUP_IDLE 0 -#define CMD_INTPR_STATUS_2D_SETUP_BUSY 1 -#define CMD_INTPR_STATUS_2D_FIFO 1:1 -#define CMD_INTPR_STATUS_2D_FIFO_NOT_EMPTY 0 -#define CMD_INTPR_STATUS_2D_FIFO_EMPTY 1 -#define CMD_INTPR_STATUS_2D_ENGINE 0:0 -#define CMD_INTPR_STATUS_2D_ENGINE_IDLE 0 -#define CMD_INTPR_STATUS_2D_ENGINE_BUSY 1 - -/* regDC.h */ -/* Panel Graphics Control */ -#define PANEL_DISPLAY_CTRL 0x080000 -#define PANEL_DISPLAY_CTRL_FPEN 27:27 -#define PANEL_DISPLAY_CTRL_FPEN_LOW 0 -#define PANEL_DISPLAY_CTRL_FPEN_HIGH 1 -#define PANEL_DISPLAY_CTRL_VBIASEN 26:26 -#define PANEL_DISPLAY_CTRL_VBIASEN_LOW 0 -#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH 1 -#define PANEL_DISPLAY_CTRL_DATA 25:25 -#define PANEL_DISPLAY_CTRL_DATA_DISABLE 0 -#define PANEL_DISPLAY_CTRL_DATA_ENABLE 1 -#define PANEL_DISPLAY_CTRL_FPVDDEN 24:24 -#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW 0 -#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH 1 -#define PANEL_DISPLAY_CTRL_PATTERN 23:23 -#define PANEL_DISPLAY_CTRL_PATTERN_4 0 -#define PANEL_DISPLAY_CTRL_PATTERN_8 1 -#define PANEL_DISPLAY_CTRL_TFT 22:21 -#define PANEL_DISPLAY_CTRL_TFT_24 0 -#define PANEL_DISPLAY_CTRL_TFT_9 1 -#define PANEL_DISPLAY_CTRL_TFT_12 2 -#define PANEL_DISPLAY_CTRL_DITHER 20:20 -#define PANEL_DISPLAY_CTRL_DITHER_DISABLE 0 -#define PANEL_DISPLAY_CTRL_DITHER_ENABLE 1 -#define PANEL_DISPLAY_CTRL_LCD 19:18 -#define PANEL_DISPLAY_CTRL_LCD_TFT 0 -#define PANEL_DISPLAY_CTRL_LCD_STN_8 2 -#define PANEL_DISPLAY_CTRL_LCD_STN_12 3 -#define PANEL_DISPLAY_CTRL_FIFO 17:16 -#define PANEL_DISPLAY_CTRL_FIFO_1 0 -#define PANEL_DISPLAY_CTRL_FIFO_3 1 -#define PANEL_DISPLAY_CTRL_FIFO_7 2 -#define PANEL_DISPLAY_CTRL_FIFO_11 3 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 -#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 -#define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9 -#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0 -#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1 -#define PANEL_DISPLAY_CTRL_TIMING 8:8 -#define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0 -#define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN 6:6 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE 0 -#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE 1 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR 5:5 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT 0 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT 1 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0 -#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1 -#define PANEL_DISPLAY_CTRL_GAMMA 3:3 -#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define PANEL_DISPLAY_CTRL_PLANE 2:2 -#define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0 -#define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1 -#define PANEL_DISPLAY_CTRL_FORMAT 1:0 -#define PANEL_DISPLAY_CTRL_FORMAT_8 0 -#define PANEL_DISPLAY_CTRL_FORMAT_16 1 -#define PANEL_DISPLAY_CTRL_FORMAT_32 2 - -#define PANEL_PAN_CTRL 0x080004 -#define PANEL_PAN_CTRL_VERTICAL_PAN 31:24 -#define PANEL_PAN_CTRL_VERTICAL_VSYNC 21:16 -#define PANEL_PAN_CTRL_HORIZONTAL_PAN 15:8 -#define PANEL_PAN_CTRL_HORIZONTAL_VSYNC 5:0 - -#define PANEL_COLOR_KEY 0x080008 -#define PANEL_COLOR_KEY_MASK 31:16 -#define PANEL_COLOR_KEY_VALUE 15:0 - -#define PANEL_FB_ADDRESS 0x08000C -#define PANEL_FB_ADDRESS_STATUS 31:31 -#define PANEL_FB_ADDRESS_STATUS_CURRENT 0 -#define PANEL_FB_ADDRESS_STATUS_PENDING 1 -#define PANEL_FB_ADDRESS_EXT 27:27 -#define PANEL_FB_ADDRESS_EXT_LOCAL 0 -#define PANEL_FB_ADDRESS_EXT_EXTERNAL 1 -#define PANEL_FB_ADDRESS_CS 26:26 -#define PANEL_FB_ADDRESS_CS_0 0 -#define PANEL_FB_ADDRESS_CS_1 1 -#define PANEL_FB_ADDRESS_ADDRESS 25:0 - -#define PANEL_FB_WIDTH 0x080010 -#define PANEL_FB_WIDTH_WIDTH 29:16 -#define PANEL_FB_WIDTH_OFFSET 13:0 - -#define PANEL_WINDOW_WIDTH 0x080014 -#define PANEL_WINDOW_WIDTH_WIDTH 27:16 -#define PANEL_WINDOW_WIDTH_X 11:0 - -#define PANEL_WINDOW_HEIGHT 0x080018 -#define PANEL_WINDOW_HEIGHT_HEIGHT 27:16 -#define PANEL_WINDOW_HEIGHT_Y 11:0 - -#define PANEL_PLANE_TL 0x08001C -#define PANEL_PLANE_TL_TOP 26:16 -#define PANEL_PLANE_TL_LEFT 10:0 - -#define PANEL_PLANE_BR 0x080020 -#define PANEL_PLANE_BR_BOTTOM 26:16 -#define PANEL_PLANE_BR_RIGHT 10:0 - -#define PANEL_HORIZONTAL_TOTAL 0x080024 -#define PANEL_HORIZONTAL_TOTAL_TOTAL 27:16 -#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END 11:0 - -#define PANEL_HORIZONTAL_SYNC 0x080028 -#define PANEL_HORIZONTAL_SYNC_WIDTH 23:16 -#define PANEL_HORIZONTAL_SYNC_START 11:0 - -#define PANEL_VERTICAL_TOTAL 0x08002C -#define PANEL_VERTICAL_TOTAL_TOTAL 26:16 -#define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0 - -#define PANEL_VERTICAL_SYNC 0x080030 -#define PANEL_VERTICAL_SYNC_HEIGHT 21:16 -#define PANEL_VERTICAL_SYNC_START 10:0 - -#define PANEL_CURRENT_LINE 0x080034 -#define PANEL_CURRENT_LINE_LINE 10:0 - -/* CRT Graphics Control */ - -#define CRT_DISPLAY_CTRL 0x080200 -#define CRT_DISPLAY_CTRL_FIFO 17:16 -#define CRT_DISPLAY_CTRL_FIFO_1 0 -#define CRT_DISPLAY_CTRL_FIFO_3 1 -#define CRT_DISPLAY_CTRL_FIFO_7 2 -#define CRT_DISPLAY_CTRL_FIFO_11 3 -#define CRT_DISPLAY_CTRL_TV_PHASE 15:15 -#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_TV_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0 -#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1 -#define CRT_DISPLAY_CTRL_BLANK 10:10 -#define CRT_DISPLAY_CTRL_BLANK_OFF 0 -#define CRT_DISPLAY_CTRL_BLANK_ON 1 -#define CRT_DISPLAY_CTRL_SELECT 9:9 -#define CRT_DISPLAY_CTRL_SELECT_PANEL 0 -#define CRT_DISPLAY_CTRL_SELECT_CRT 1 -#define CRT_DISPLAY_CTRL_TIMING 8:8 -#define CRT_DISPLAY_CTRL_TIMING_DISABLE 0 -#define CRT_DISPLAY_CTRL_TIMING_ENABLE 1 -#define CRT_DISPLAY_CTRL_PIXEL 7:4 -#define CRT_DISPLAY_CTRL_GAMMA 3:3 -#define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0 -#define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1 -#define CRT_DISPLAY_CTRL_PLANE 2:2 -#define CRT_DISPLAY_CTRL_PLANE_DISABLE 0 -#define CRT_DISPLAY_CTRL_PLANE_ENABLE 1 -#define CRT_DISPLAY_CTRL_FORMAT 1:0 -#define CRT_DISPLAY_CTRL_FORMAT_8 0 -#define CRT_DISPLAY_CTRL_FORMAT_16 1 -#define CRT_DISPLAY_CTRL_FORMAT_32 2 - -#define CRT_FB_ADDRESS 0x080204 -#define CRT_FB_ADDRESS_STATUS 31:31 -#define CRT_FB_ADDRESS_STATUS_CURRENT 0 -#define CRT_FB_ADDRESS_STATUS_PENDING 1 -#define CRT_FB_ADDRESS_EXT 27:27 -#define CRT_FB_ADDRESS_EXT_LOCAL 0 -#define CRT_FB_ADDRESS_EXT_EXTERNAL 1 -#define CRT_FB_ADDRESS_CS 26:26 -#define CRT_FB_ADDRESS_CS_0 0 -#define CRT_FB_ADDRESS_CS_1 1 -#define CRT_FB_ADDRESS_ADDRESS 25:0 - -#define CRT_FB_WIDTH 0x080208 -#define CRT_FB_WIDTH_WIDTH 29:16 -#define CRT_FB_WIDTH_OFFSET 13:0 - -#define CRT_HORIZONTAL_TOTAL 0x08020C -#define CRT_HORIZONTAL_TOTAL_TOTAL 27:16 -#define CRT_HORIZONTAL_TOTAL_DISPLAY_END 11:0 - -#define CRT_HORIZONTAL_SYNC 0x080210 -#define CRT_HORIZONTAL_SYNC_WIDTH 23:16 -#define CRT_HORIZONTAL_SYNC_START 11:0 - -#define CRT_VERTICAL_TOTAL 0x080214 -#define CRT_VERTICAL_TOTAL_TOTAL 26:16 -#define CRT_VERTICAL_TOTAL_DISPLAY_END 10:0 - -#define CRT_VERTICAL_SYNC 0x080218 -#define CRT_VERTICAL_SYNC_HEIGHT 21:16 -#define CRT_VERTICAL_SYNC_START 10:0 - -#define CRT_SIGNATURE_ANALYZER 0x08021C -#define CRT_SIGNATURE_ANALYZER_STATUS 31:16 -#define CRT_SIGNATURE_ANALYZER_ENABLE 3:3 -#define CRT_SIGNATURE_ANALYZER_ENABLE_DISABLE 0 -#define CRT_SIGNATURE_ANALYZER_ENABLE_ENABLE 1 -#define CRT_SIGNATURE_ANALYZER_RESET 2:2 -#define CRT_SIGNATURE_ANALYZER_RESET_NORMAL 0 -#define CRT_SIGNATURE_ANALYZER_RESET_RESET 1 -#define CRT_SIGNATURE_ANALYZER_SOURCE 1:0 -#define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 -#define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 -#define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 - -#define CRT_CURRENT_LINE 0x080220 -#define CRT_CURRENT_LINE_LINE 10:0 - -#define CRT_MONITOR_DETECT 0x080224 -#define CRT_MONITOR_DETECT_ENABLE 24:24 -#define CRT_MONITOR_DETECT_ENABLE_DISABLE 0 -#define CRT_MONITOR_DETECT_ENABLE_ENABLE 1 -#define CRT_MONITOR_DETECT_RED 23:16 -#define CRT_MONITOR_DETECT_GREEN 15:8 -#define CRT_MONITOR_DETECT_BLUE 7:0 - -/* CRT Cursor Control */ -#define CRT_HWC_ADDRESS 0x080230 -#define CRT_HWC_ADDRESS_ENABLE 31:31 -#define CRT_HWC_ADDRESS_ENABLE_DISABLE 0 -#define CRT_HWC_ADDRESS_ENABLE_ENABLE 1 -#define CRT_HWC_ADDRESS_EXT 27:27 -#define CRT_HWC_ADDRESS_EXT_LOCAL 0 -#define CRT_HWC_ADDRESS_EXT_EXTERNAL 1 -#define CRT_HWC_ADDRESS_CS 26:26 -#define CRT_HWC_ADDRESS_CS_0 0 -#define CRT_HWC_ADDRESS_CS_1 1 -#define CRT_HWC_ADDRESS_ADDRESS 25:0 - -#define CRT_HWC_LOCATION 0x080234 -#define CRT_HWC_LOCATION_TOP 27:27 -#define CRT_HWC_LOCATION_TOP_INSIDE 0 -#define CRT_HWC_LOCATION_TOP_OUTSIDE 1 -#define CRT_HWC_LOCATION_Y 26:16 -#define CRT_HWC_LOCATION_LEFT 11:11 -#define CRT_HWC_LOCATION_LEFT_INSIDE 0 -#define CRT_HWC_LOCATION_LEFT_OUTSIDE 1 -#define CRT_HWC_LOCATION_X 10:0 - -#define CRT_HWC_COLOR_12 0x080238 -#define CRT_HWC_COLOR_12_2_RGB565 31:16 -#define CRT_HWC_COLOR_12_1_RGB565 15:0 - -#define CRT_HWC_COLOR_3 0x08023C -#define CRT_HWC_COLOR_3_RGB565 15:0 - -#define CRT_HWC_COLOR_01 0x080238 -#define CRT_HWC_COLOR_01_1_RED 31:27 -#define CRT_HWC_COLOR_01_1_GREEN 26:21 -#define CRT_HWC_COLOR_01_1_BLUE 20:16 -#define CRT_HWC_COLOR_01_0_RED 15:11 -#define CRT_HWC_COLOR_01_0_GREEN 10:5 -#define CRT_HWC_COLOR_01_0_BLUE 4:0 - -#define CRT_HWC_COLOR_2 0x08023C -#define CRT_HWC_COLOR_2_RED 15:11 -#define CRT_HWC_COLOR_2_GREEN 10:5 -#define CRT_HWC_COLOR_2_BLUE 4:0 -#define CRT_PALETTE_RAM 0x080400 -#define PANEL_PALETTE_RAM 0x080800 -#define VIDEO_PALETTE_RAM 0x080C00 +Bool SMI501_EnterVT(int scrnIndex, int flags); +void SMI501_LeaveVT(int scrnIndex, int flags); +void SMI501_Save(ScrnInfoPtr pScrn); +void SMI501_DisplayPowerManagementSet(ScrnInfoPtr pScrn, + int PowerManagementMode, int flags); +Bool SMI501_ModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode); -#endif /*_SMI_H*/ +#endif /*_SMI_501_H*/ |