diff options
| author | Egbert Eich <eich@linux-21vw.site> | 2009-07-01 14:06:27 +0200 |
|---|---|---|
| committer | Egbert Eich <eich@freedesktop.org> | 2009-10-07 16:06:33 +0200 |
| commit | 3cef2a6553359b063b760a2f436ce84365c60682 (patch) | |
| tree | 950d432582a5d405f139e8f7334a95087fae2a0d | |
| parent | 392a13923eb4d44a8bdb204922230e126b188fae (diff) | |
Improve test for disabled differential clock driver.
| -rw-r--r-- | src/rhd_pll.c | 8 | ||||
| -rw-r--r-- | src/rhd_regs.h | 2 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/rhd_pll.c b/src/rhd_pll.c index 5b8d2bb..6200dda 100644 --- a/src/rhd_pll.c +++ b/src/rhd_pll.c @@ -733,8 +733,10 @@ RV620PLL1Power(struct rhdPLL *PLL, int Power) usleep(2); /* Sometimes we have to keep unused PLL running, see bug #18016 */ - if ((RHDRegRead(PLL, RV620_EXT1_DIFF_POST_DIV_CNTL) & 0x0100) == 0) + if ((RHDRegRead(PLL, RV620_EXT1_DIFF_POST_DIV_CNTL) & RV62_EXT1_DIFF_DRIVER_ENABLE) == 0) RHDRegMask(PLL, P1PLL_CNTL, 0x02, 0x02); /* Power down */ + else + xf86DrvMsg(PLL->scrnIndex, X_WARNING, "PHYA differential clock driver not disabled\n"); usleep(200); RHDRegMask(PLL, P1PLL_CNTL, 0x2000, 0x2000); /* reset anti-glitch */ @@ -786,8 +788,10 @@ RV620PLL2Power(struct rhdPLL *PLL, int Power) usleep(2); /* Sometimes we have to keep unused PLL running, see bug #18016 */ - if ((RHDRegRead(PLL, RV620_EXT2_DIFF_POST_DIV_CNTL) & 0x0100) == 0) + if ((RHDRegRead(PLL, RV620_EXT2_DIFF_POST_DIV_CNTL) & RV62_EXT2_DIFF_DRIVER_ENABLE) == 0) RHDRegMask(PLL, P2PLL_CNTL, 0x02, 0x02); /* Power down */ + else + xf86DrvMsg(PLL->scrnIndex, X_WARNING, "PHYB differential clock driver not disabled\n"); usleep(200); RHDRegMask(PLL, P2PLL_CNTL, 0x2000, 0x2000); /* reset anti-glitch */ diff --git a/src/rhd_regs.h b/src/rhd_regs.h index 0a1e0c8..3ca5e98 100644 --- a/src/rhd_regs.h +++ b/src/rhd_regs.h @@ -516,7 +516,7 @@ enum RV620_EXT1_DIFF_POST_DIV_CNTL_BITS { enum RV620_EXT2_DIFF_POST_DIV_CNTL_BITS { RV62_EXT2_DIFF_POST_DIV_RESET = 1 << 0, RV62_EXT2_DIFF_POST_DIV_SELECT = 1 << 4, - RV62_EXT2_DIFF_DRIVER_ENABLE = 1 << 8 + RV62_EXT2_DIFF_DRIVER_ENABLE = 3 << 8 }; enum RV620_LVTMA_PWRSEQ_CNTL_BITS { |