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2011-08-09NEWS: 2.16.0 release2.16.0Chris Wilson2-1/+12
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-08-01Fix man page formattingEdward Sheldrake1-0/+2
Two option sections were not starting at the beginning of a new line.
2011-08-01dri: Build fix for xserver-1.7.7Chris Wilson1-0/+13
Back in the olden days before the introduction of dixRegisterPrivate(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-30NEWS: 2.15.901 snapshot2.15.901Chris Wilson2-1/+31
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-30Fix typos for distcheckChris Wilson2-2/+3
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-30sna: Mark the stencil as untiledChris Wilson1-3/+13
In reality, Mesa will be treating it as W-tiling, only we have no way of communicating that requirement to the kernel (as not only does the kernel not understand W-tiling, but also the GTT is incapable of fencing a W-tiled region.). Ported from Chad Versace's 3e55f3e88. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-30sna: Port IVB acceleration code (Xrender + Xv)Chris Wilson6-2/+4815
Based on the superlative work by Kenneth Graunke and Xiang, Haihao. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-30sna: Include the pixmap size in the debug info for moving to cpuChris Wilson1-1/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Enable RENDER acceleration on Ivybridge.Kenneth Graunke1-3/+0
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Update pixel shader state for Ivybridge.Kenneth Graunke1-3/+35
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Use Ivybridge variants for 3D pipeline setup.Kenneth Graunke1-11/+39
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Refactor to use newly shared pipeline setup code in i965_3d.c.Kenneth Graunke4-185/+44
Slightly generalize the shared SF and CC code to accomodate both. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28Xv: Refactor out pipeline setup functions for future reuse in render.Kenneth Graunke4-478/+482
While we're at it, make the functions simply take an intel_screen_private pointer directly instead of having to fetch it from ScrnInfoPtr. Also coalesce some gen6/gen7 functions that were 98% identical. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Update 3DPRIMITIVE for Ivybridge.Kenneth Graunke1-5/+11
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Set Address Modify Enable in 3DSTATE_VERTEX_BUFFERS on Gen7.Kenneth Graunke1-0/+5
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Update SAMPLER_STATE for Ivybridge.Kenneth Graunke1-9/+124
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: Update SURFACE_STATE for Ivybridge.Kenneth Graunke1-9/+82
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28render: New Ivybridge assembly programs for render acceleration.Kenneth Graunke14-3/+454
These are exactly the same as the ones for Sandybridge, but with message registers translated (hopefully) in the same way as Haihao's new programs (m1 == g65). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-26sna: Revert enabling scan-line wait on SNBChris Wilson1-0/+4
Hanging the machine does indeed prevent video tearing. Just not quite what the user expected... Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=39497 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-20sna: Enable gen6 scan-line waitingChris Wilson1-5/+16
The code was ready and waiting, just forgot to turn it on. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-19dri: Do not tile stencil bufferChad Versace1-4/+12
Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT is incapable of W fencing, so we allocate the stencil buffer with I915_TILING_NONE and decode the tile's layout in software. This commit mutually depends on the mesa commit: intel: Fix stencil buffer to be W tiled Author: Chad Versace <chad@chad-versace.us> Date: Mon Jul 18 00:37:45 2011 -0700 Signed-off-by: Chad Versace <chad@chad-versace.us> Reviewed-by: Ian Romanick <ian.romanick@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2011-07-13Disable adding normal RTF modes for an eDPChris Wilson1-1/+6
This is causing a hard hang with 2.6.39+, we don't know why so play safe and disable for the time being. References: https://bugs.freedesktop.org/show_bug.cgi?id=38012 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna: Fast-path single span boxesChris Wilson4-1/+49
These are very common when compositing unclipped trapezoids, and the majority of the overhead is in handling the arbitrary number of boxes and misses out on the constant folding the compiler can do if it is known we have just one box. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna/damage: Avoid testing against a completey damaged regionChris Wilson6-17/+52
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna/gen3: Tune emit_spans_primitive_constantChris Wilson1-9/+3
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna/glyphs: Discard GLYPH_PICTURE hint if the glyph doesn't fit into the cacheChris Wilson1-1/+3
If the glyph is too big to fit into the cache, than ideally we do want to keep an associated GPU bo around for future use. As it is too large to fit into the cache, it of reasonable size and there is little wastage in allocating indiviual GPU bo for each oversized glyph. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna: Add some extra debugging to the texture upload fallback pathsChris Wilson1-3/+7
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna/dri: Fix a couple of typosChris Wilson1-2/+2
Somehow these were lost in the rebasing. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-13sna/dri: Remove the unused id/type members for Resource trackingChris Wilson1-20/+12
...and reduce it to a simple list. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-12dri: Always initialise resource members of DRI2FrameEventChris Wilson2-0/+20
As we now attempt to always decouple the lists upon freeing the frame event, we need to initialise them along all code paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-11sna/dri: Add some simple debuggingChris Wilson1-1/+13
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-11sna/dri: Refactor common code for assigning a pixmap to the DRI2 bufferChris Wilson1-18/+15
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-11dri: Enable triple-bufferred pageflipsChris Wilson5-125/+217
By popular demand. Triple-buffering trade-offs output latency versus jitter. By having a pre-rendered frame ready to swap in following a pageflip, we avoid the scenario where the latency between receiving the flip complete signal from the kernel, waking up the vsynced application, it render the new frame and then for the server to process the swap request is greater than the frame interval, causing us to miss the vblank. The result is that application can become frame-locked to 30fps. Instead, we report to the application that the first frame swap is immediately completed, supply a new back buffer (or else the rendering would be blocked on waiting for the front-buffer to be swapped away from the scanout) and let them proceed to render the second frame. The second frame is added to the swap queue, and the client throttled to vrefresh. (If the client missed the vblank, the swap queue is empty and the client is immediately woken again, whilst the pageflip is pending.) Note, for practical reasons this only applies to page-flipping, for example, calls to glXSwapBuffer() on fullscreen applications. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-11dri: Prevent abuse of the Resource databaseChris Wilson3-42/+176
The Resource database is only designed to store a single value for a particular type associated with an XID. Due to the asynchronous nature of the vblank/flip requests, we would often associate multiple frame events with a particular drawable/client. Upon freeing the resource, we would not necessarily decouple the right value, leaving a stale pointer behind. Later when the client disappeared, we would write through that stale pointer upsetting valgrind and causing memory corruption. MDK. Instead, we need to implement an extra layer for tracking multiple frames within a single Resource. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37700 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-09dri: Remove the shadow copy of attachmentChris Wilson1-5/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-09sna: Clamp results for computing BoxRec coords from xRectangleChris Wilson2-28/+59
As the width/height in the rectangle is specified as uint16_t, the result may be larger than is storagable in the int16_t of the box. Of course it would take a really inane client to do attempt to draw something much larger than the largest possible surface... Is it strange that first example I've found to do so is a Java application? Reported-by: Nicolas Kalkhof <nkalkhof@web.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-09sna/accel: Fix fallback for depth=1 copyChris Wilson1-11/+19
A little carelessness with passing down the offsets caused us to incorrectly copy depth=1 bitmaps, as exemplified by gkrellm. Reported-by: Nicolas Kalkhof <nkalkhof@web.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-08sna: A buffer only needs a flush if it remains dirty at the end of the batchChris Wilson3-4/+8
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-08sna/gen3: So we also need to ensure stippling is cleared...Chris Wilson1-1/+4
My theory that we used nothing that invoked polygon stippling proved baseless. Fixes regression from 3b5971bd2359383cb8326702d80e03bc15d34c69 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-08sna/gen3: Restore disabling the use of stencil/fog in the invariantChris Wilson1-2/+3
One cleanup too far causing spurious results after rebooting. We also need to ensure that the writemask is fully enabled (ie not disabled) as well. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-08sna/dri: Enable chaining of page-flipsChris Wilson1-38/+135
Trade off extra frames of latency for extra frames of anti-jitter buffering and loss of completion information; compiz users rejoice. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-07sna/dri: Remove redundant NULL check in referenceChris Wilson1-4/+2
The buffer has already been dereferenced by this point... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-07sna: Take advantage of the needs_flush tracking on the front bufferChris Wilson2-0/+11
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-06sna: Check against an execbuffer reference before discarding partialsChris Wilson1-2/+2
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-06sna: Compute aligned tiled heights for gen2 correctlyChris Wilson1-3/+6
We were underestimating the height of X-tiled surfaces (and less harmfully overestimating the height of Y-tiled surfaces.) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-05sna: Reset unused partial buffersChris Wilson1-55/+61
Whilst searching for available space on the active partial buffer list, if we discover an unreferenced one, reset its used counter to zero. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-05sna: Discard unused partial buffersChris Wilson1-1/+26
If we allocate a partial buffer and then fallback for the operation, the buffer would remain on the partial list waiting for another user. Discard any unused partials at the next batch submission or expiration point. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-05sna/gen2: Restore invariant ENABLESChris Wilson1-0/+18
One deletion too many, unnoticed until the next reboot. Besides the failure to disable logic op and enable colour buffer blending which causes a hang if you subsequently try to enable both, you also need to request texture caching... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-05sna/gen[23]: Do as the comments suggest and prefer the BLTChris Wilson2-13/+5
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-05sna: Reduce tiling if pitch is less than a tile_width/height only on pre-G33Chris Wilson1-19/+25
(Note this only applies to 2D pixmaps.) The rationale, borne out by experimentation with cairo-perf-trace, is that on the pre-G33 devices we always need a fence region region for tiled surfaces, i.e. at least .5/1MiB in size, and that combined with the smaller GTT on those devices, we loose the benefit of tiling to the excessive GTT thrashing. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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