diff options
Diffstat (limited to 'src/i830_exa.c')
| -rw-r--r-- | src/i830_exa.c | 69 |
1 files changed, 50 insertions, 19 deletions
diff --git a/src/i830_exa.c b/src/i830_exa.c index 4944e409..f1cd1e36 100644 --- a/src/i830_exa.c +++ b/src/i830_exa.c @@ -345,9 +345,9 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, int vertex_count; if (pMask) - vertex_count = 4*6; + vertex_count = 3*6; else - vertex_count = 4*4; + vertex_count = 3*4; BEGIN_LP_RING(6+vertex_count); @@ -357,7 +357,7 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, OUT_RING(MI_NOOP); OUT_RING(MI_NOOP); - OUT_RING(PRIM3D_INLINE | PRIM3D_TRIFAN | (vertex_count-1)); + OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST | (vertex_count-1)); OUT_RING_F(dstX); OUT_RING_F(dstY); @@ -385,15 +385,6 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, OUT_RING_F(maskXend / pI830->scale_units[1][0]); OUT_RING_F(maskYend / pI830->scale_units[1][1]); } - - OUT_RING_F(dstX + w); - OUT_RING_F(dstY); - OUT_RING_F(srcXend / pI830->scale_units[0][0]); - OUT_RING_F(srcY / pI830->scale_units[0][1]); - if (pMask) { - OUT_RING_F(maskXend / pI830->scale_units[1][0]); - OUT_RING_F(maskY / pI830->scale_units[1][1]); - } ADVANCE_LP_RING(); } } @@ -447,13 +438,53 @@ I830EXAInit(ScreenPtr pScreen) /* disable Xv here... */ } - /* i915 3D requires 16 byte alignment (4k if tiled) */ - pI830->EXADriverPtr->pixmapOffsetAlign = 256; - pI830->EXADriverPtr->pixmapPitchAlign = 64; - - /* i845 and i945 2D limits rendering to 65536 lines and pitch of 32768. */ - pI830->EXADriverPtr->maxX = 4095; - pI830->EXADriverPtr->maxY = 4095; + /* Limits are described in the BLT engine chapter under Graphics Data Size + * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO, + * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO. + * + * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768. + * + * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled. + * i965 limits 3D surface to 4kB-aligned offset if tiled. + * i965 limits 3D surfaces to w,h of ?,8192. + * i965 limits 3D surface to pitch of 1B - 128kB. + * i965 limits 3D surface pitch alignment to 512B, only if tiled. + * i965 limits 3D destination drawing rect to w,h of 8192,8192. + * + * i915 limits 3D textures to 4B-aligned offset if un-tiled. + * i915 limits 3D textures to ~4kB-aligned offset if tiled. + * i915 limits 3D textures to width,height of 2048,2048. + * i915 limits 3D textures to pitch of 16B - 8kB, in dwords. + * i915 limits 3D destination to ~4kB-aligned offset if tiled. + * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled. + * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled. + * i915 limits 3D destination to POT aligned pitch if tiled. + * i915 limits 3D destination drawing rect to w,h of 2048,2048. + * + * i845 limits 3D textures to 4B-aligned offset if un-tiled. + * i845 limits 3D textures to ~4kB-aligned offset if tiled. + * i845 limits 3D textures to width,height of 2048,2048. + * i845 limits 3D textures to pitch of 4B - 8kB, in dwords. + * i845 limits 3D destination to 4B-aligned offset if un-tiled. + * i845 limits 3D destination to ~4kB-aligned offset if tiled. + * i845 limits 3D destination to pitch of 8B - 8kB, in dwords. + * i845 limits 3D destination drawing rect to w,h of 2048,2048. + * + * For the tiled issues, the only tiled buffer we draw to should be + * the front, which will have an appropriate pitch/offset already set up, + * so EXA doesn't need to worry. + */ + if (IS_I965G(pI830)) { + pI830->EXADriverPtr->pixmapOffsetAlign = 4 * 2; + pI830->EXADriverPtr->pixmapPitchAlign = 1; + pI830->EXADriverPtr->maxX = 8192; + pI830->EXADriverPtr->maxY = 8192; + } else { + pI830->EXADriverPtr->pixmapOffsetAlign = 4; + pI830->EXADriverPtr->pixmapPitchAlign = 16; + pI830->EXADriverPtr->maxX = 2048; + pI830->EXADriverPtr->maxY = 2048; + } /* Sync */ pI830->EXADriverPtr->WaitMarker = I830EXASync; |