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authorChris Wilson <chris@chris-wilson.co.uk>2013-07-26 09:35:06 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2013-07-28 14:49:07 +0100
commit45d4e8dcf9aee37015b1ee026997ed4dabdf112e (patch)
treec140efa6a28d80266849d08d5ea368419e95c977 /xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i
parentab28526ea43728fb675448515e1519a970fb5f56 (diff)
uxa: Clear up the common intel directory
Move all the UXA backend specifc files into their own subdirectory. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i')
-rw-r--r--xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i71
1 files changed, 71 insertions, 0 deletions
diff --git a/xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i b/xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i
new file mode 100644
index 00000000..96aada87
--- /dev/null
+++ b/xvmc/shader/mc/read_frame_x1y1_uv_igd.g4i
@@ -0,0 +1,71 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Author:
+ * Zou Nan hai <nanhai.zou@intel.com>
+ * Zhang Hua jun <huajun.zhang@intel.com>
+ * Xing Dong sheng <dongsheng.xing@intel.com>
+ *
+ */
+send (16) 0 g86.0<1>UW g2<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 4 {align1};
+send (16) 0 g94.0<1>UW g2<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 4 {align1};
+mov (1) g2.8<1>UD 0x01001FUD {align1};
+add (1) g2.4<1>UD g2.4<1,1,1>UD 8D {align1};
+send (16) 0 g90.0<1>UW g2<8,8,1>UW read(input_surface1, 2, 0, 2) mlen 1 rlen 1 {align1};
+send (16) 0 g98.0<1>UW g2<8,8,1>UW read(input_surface2, 2, 0, 2) mlen 1 rlen 1 {align1};
+mov (1) g2.8<1>UD 0x007000fUD {align1};
+
+add (16) g44.0<1>UW g86.0<16,8,1>UB g86.1<16,8,1>UB{align1};
+add (16) g45.0<1>UW g87.0<16,8,1>UB g87.1<16,8,1>UB{align1};
+add (16) g46.0<1>UW g88.0<16,8,1>UB g88.1<16,8,1>UB{align1};
+add (16) g47.0<1>UW g89.0<16,8,1>UB g89.1<16,8,1>UB{align1};
+add (16) g44.0<1>UW g44.0<16,16,1>UW g87.0<16,8,1>UB{align1};
+add (16) g45.0<1>UW g45.0<16,16,1>UW g88.0<16,8,1>UB{align1};
+add (16) g46.0<1>UW g46.0<16,16,1>UW g89.0<16,8,1>UB{align1};
+add (16) g47.0<1>UW g47.0<16,16,1>UW g90.0<16,8,1>UB{align1};
+
+add (16) g44.0<1>UW g44.0<16,16,1>UW g87.1<16,8,1>UB{align1};
+add (16) g45.0<1>UW g45.0<16,16,1>UW g88.1<16,8,1>UB{align1};
+add (16) g46.0<1>UW g46.0<16,16,1>UW g89.1<16,8,1>UB{align1};
+add (16) g47.0<1>UW g47.0<16,16,1>UW g90.1<16,8,1>UB{align1};
+add (16) g48.0<1>UW g94.0<16,8,1>UB g95.0<16,8,1>UB{align1};
+add (16) g49.0<1>UW g95.0<16,8,1>UB g96.0<16,8,1>UB{align1};
+add (16) g50.0<1>UW g96.0<16,8,1>UB g97.0<16,8,1>UB{align1};
+add (16) g51.0<1>UW g97.0<16,8,1>UB g98.0<16,8,1>UB{align1};
+
+add (16) g48.0<1>UW g48.0<16,16,1>UW g94.1<16,8,1>UB{align1};
+add (16) g49.0<1>UW g49.0<16,16,1>UW g95.1<16,8,1>UB{align1};
+add (16) g50.0<1>UW g50.0<16,16,1>UW g96.1<16,8,1>UB{align1};
+add (16) g51.0<1>UW g51.0<16,16,1>UW g97.1<16,8,1>UB{align1};
+add (16) g48.0<1>UW g48.0<16,16,1>UW g95.1<16,8,1>UB{align1};
+add (16) g49.0<1>UW g49.0<16,16,1>UW g96.1<16,8,1>UB{align1};
+add (16) g50.0<1>UW g50.0<16,16,1>UW g97.1<16,8,1>UB{align1};
+add (16) g51.0<1>UW g51.0<16,16,1>UW g98.1<16,8,1>UB{align1};
+
+shr.sat (16) g44.0<1>UW g44.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g45.0<1>UW g45.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g46.0<1>UW g46.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g47.0<1>UW g47.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g48.0<1>UW g48.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g49.0<1>UW g49.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g50.0<1>UW g50.0<16,16,1>UW 2UW {align1};
+shr.sat (16) g51.0<1>UW g51.0<16,16,1>UW 2UW {align1};