diff options
| author | Keith Packard <keithp@keithp.com> | 2009-05-07 14:58:01 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-05-12 14:38:29 -0700 |
| commit | ff7494b4c4b1bd8bb6f169402a9edbe9780787bb (patch) | |
| tree | 0d56f093f0c67d540910b0a285e08f9b34dce20e | |
| parent | e54a23bff068416ccbdb75d538dc7dcd40a6c95c (diff) | |
Add DP link and GMCH M and N registers
Signed-off-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | src/i810_reg.h | 42 | ||||
| -rw-r--r-- | src/i830_debug.c | 8 |
2 files changed, 50 insertions, 0 deletions
diff --git a/src/i810_reg.h b/src/i810_reg.h index 8d4e6418..cb337842 100644 --- a/src/i810_reg.h +++ b/src/i810_reg.h @@ -2214,6 +2214,43 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PIPE_PIXEL_MASK 0x00ffffff #define PIPE_PIXEL_SHIFT 0 +/* + * Computing GMCH M and N values. + * + * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes + * + * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) + * + * The GMCH value is used internally + */ +#define PIPEA_GMCH_DATA_M 0x70050 + +/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ +#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) +#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 + +#define PIPE_GMCH_DATA_M_MASK (0xffffff) + +#define PIPEA_GMCH_DATA_N 0x70054 +#define PIPE_GMCH_DATA_N_MASK (0xffffff) + +/* + * Computing Link M and N values. + * + * Link M / N = pixel_clock / ls_clk + * + * (the DP spec calls pixel_clock the 'strm_clk') + * + * The Link value is transmitted in the Main Stream + * Attributes and VB-ID. + */ + +#define PIPEA_DP_LINK_M 0x70060 +#define PIPEA_DP_LINK_M_MASK (0xffffff) + +#define PIPEA_DP_LINK_N 0x70064 +#define PIPEA_DP_LINK_N_MASK (0xffffff) + #define PIPEB_DSL 0x71000 #define PIPEBCONF 0x71008 @@ -2231,6 +2268,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PIPEBFRAMEHIGH 0x71040 #define PIPEBFRAMEPIXEL 0x71044 +#define PIPEB_GMCH_DATA_M 0x71050 +#define PIPEB_GMCH_DATA_N 0x71054 +#define PIPEB_DP_LINK_M 0x71060 +#define PIPEB_DP_LINK_N 0x71064 + #define DSPACNTR 0x70180 #define DSPBCNTR 0x71180 #define DISPLAY_PLANE_ENABLE (1<<31) diff --git a/src/i830_debug.c b/src/i830_debug.c index 86f5f21d..5a8c3eb5 100644 --- a/src/i830_debug.c +++ b/src/i830_debug.c @@ -652,6 +652,10 @@ static struct i830SnapshotRec { DEFINEREG2(PIPEACONF, i830_debug_pipeconf), DEFINEREG2(PIPEASRC, i830_debug_yxminus1), DEFINEREG2(PIPEASTAT, i830_debug_pipestat), + DEFINEREG(PIPEA_GMCH_DATA_M), + DEFINEREG(PIPEA_GMCH_DATA_N), + DEFINEREG(PIPEA_DP_LINK_M), + DEFINEREG(PIPEA_DP_LINK_N), DEFINEREG2(FPA0, i830_debug_fp), DEFINEREG2(FPA1, i830_debug_fp), @@ -676,6 +680,10 @@ static struct i830SnapshotRec { DEFINEREG2(PIPEBCONF, i830_debug_pipeconf), DEFINEREG2(PIPEBSRC, i830_debug_yxminus1), DEFINEREG2(PIPEBSTAT, i830_debug_pipestat), + DEFINEREG(PIPEB_GMCH_DATA_M), + DEFINEREG(PIPEB_GMCH_DATA_N), + DEFINEREG(PIPEB_DP_LINK_M), + DEFINEREG(PIPEB_DP_LINK_N), DEFINEREG2(FPB0, i830_debug_fp), DEFINEREG2(FPB1, i830_debug_fp), |