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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-03-29 18:02:24 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2011-03-29 18:02:50 +0200 |
| commit | f660df2cb44b310740ed850037ff37891b671f28 (patch) | |
| tree | 8fe2ba7986ee27147a56735edbaa4a36ffeb35ad | |
| parent | a2c8442fcb29ef2d0df41518952a2d8df1671070 (diff) | |
Cleanup gen2 tiling confusion
A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | src/intel_uxa.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index 13d8cf93..662bcc7e 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -197,13 +197,12 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, if (*tiling != I915_TILING_NONE) { int aligned_h, tile_height; - if (*tiling == I915_TILING_X) + if (IS_GEN2(intel)) + tile_height = 16; + else if (*tiling == I915_TILING_X) tile_height = 8; else tile_height = 32; - /* i8xx has a 2-row interleaved tile layout */ - if (IS_GEN2(intel)) - tile_height *= 2; aligned_h = ALIGN(h, tile_height); *stride = intel_get_fence_pitch(intel, |