diff options
| author | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-09-26 09:44:59 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyu.z.wang@intel.com> | 2008-09-26 09:44:59 +0800 |
| commit | d8a007b056e3d6c3e132ecac06368b21d2ac4123 (patch) | |
| tree | 48bfe3fe31d419e9f28e328418cd3c6f8f87a2ff | |
| parent | a428892b76dba4c55e2ae28933d30e98d9fd646d (diff) | |
Bug #16515: Fix VT switch with DVI on G45
On DVI, centered VGA mode is used instead of native mode VGA, and
PLL on pipe is used instead of VGA PLL setting. So make sure PLL
settled down in restore time.
| -rw-r--r-- | src/i830_driver.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/i830_driver.c b/src/i830_driver.c index 9bf0a64f..1317c1d1 100644 --- a/src/i830_driver.c +++ b/src/i830_driver.c @@ -2359,12 +2359,15 @@ RestoreHWState(ScrnInfoPtr pScrn) /* If the pipe A PLL is active, we can restore the pipe & plane config */ if (pI830->saveDPLL_A & DPLL_VCO_ENABLE) { + OUTREG(FPA0, pI830->saveFPA0); OUTREG(DPLL_A, pI830->saveDPLL_A & ~DPLL_VCO_ENABLE); + POSTING_READ(DPLL_A); usleep(150); } OUTREG(FPA0, pI830->saveFPA0); OUTREG(FPA1, pI830->saveFPA1); OUTREG(DPLL_A, pI830->saveDPLL_A); + POSTING_READ(DPLL_A); i830_dpll_settle(); if (IS_I965G(pI830)) OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD); @@ -2420,12 +2423,15 @@ RestoreHWState(ScrnInfoPtr pScrn) /* If the pipe B PLL is active, we can restore the pipe & plane config */ if (pI830->saveDPLL_B & DPLL_VCO_ENABLE) { + OUTREG(FPB0, pI830->saveFPB0); OUTREG(DPLL_B, pI830->saveDPLL_B & ~DPLL_VCO_ENABLE); + POSTING_READ(DPLL_B); usleep(150); } OUTREG(FPB0, pI830->saveFPB0); OUTREG(FPB1, pI830->saveFPB1); OUTREG(DPLL_B, pI830->saveDPLL_B); + POSTING_READ(DPLL_B); i830_dpll_settle(); if (IS_I965G(pI830)) OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD); |