[965-xvmc] add missing g4a file

2 files changed, 69 insertions, 8 deletions

diff --git a/src/xvmc/null.g4a b/src/xvmc/null.g4a
new file mode 100644
index 00000000..65698426
--- /dev/null
+++ b/src/xvmc/null.g4a
@@ -0,0 +1,57 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Author:
+ *    Zou Nan hai <nanhai.zou@intel.com>
+ *
+ */
+mov (8) g3.0<1>UD g1.0<8,8,1>UD {align1};
+
+mov (16) g8.0<1>UD 0xFFFFFFFFUD {align1 compr};
+
+mov(1) g1.8<1>UD 0x0070007UD  { align1 };
+mov (16) m1<1>UD g8.0<8,8,1>UD {align1 compr};
+
+/*Write 8x8 block to (x,y)*/
+send (16) 0 acc0<1>UW g1<8,8,1>UW write(0, 0, 2, 0) mlen 3 rlen 0 { align1 };
+
+add (1) g1.0<1>UD g3.0<1,1,1>UD 0x8UD {align1};
+/*Write 8x8 block to (x+8,y)*/
+send (16) 0 acc0<1>UW g1<8,8,1>UW write(0, 0, 2, 0) mlen 3 rlen 0 { align1 };
+
+add (1) g1.4<1>UD g3.4<1,1,1>UD 0x8UD {align1};
+/*Write 8x8 block to (x+8,y+8)*/
+send (16) 0 acc0<1>UW g1<8,8,1>UW write(0, 0, 2, 0) mlen 3 rlen 0 { align1 };
+
+mov (1) g1.0<1>UD g3.0<1,1,1>UD {align1};
+/*Write 8x8 block to (x,y+8)*/
+send (16) 0 acc0<1>UW g1<8,8,1>UW write(0, 0, 2, 0) mlen 3 rlen 0 { align1 };
+
+/*Fill U buffer & V buffer with 0x7F*/
+mov (16) m1<1>UD 0x7f7f7f7fUD {align1 compr};
+shr (1) g1.0<1>UD g3.0<1,1,1>UD 1D {align1};
+shr (1) g1.4<1>UD g3.4<1,1,1>UD 1D {align1};
+send (16) 0 acc0<1>UW g1<8,8,1>UW write(2, 0, 2, 0) mlen 3 rlen 0 { align1 };
+send (16) 0 acc0<1>UW g1<8,8,1>UW write(1, 0, 2, 0) mlen 3 rlen 0 { align1 };
+
+send (16) 0 acc0<1>UW g0<8,8,1>UW 
+	thread_spawner(0, 0, 0) mlen 1 rlen 0 { align1 EOT};
diff --git a/src/xvmc/null.g4b b/src/xvmc/null.g4b
index 943f40ba..960fda9a 100644
--- a/src/xvmc/null.g4b
+++ b/src/xvmc/null.g4b
@@ -1,13 +1,17 @@
    { 0x00600001, 0x20600021, 0x008d0020, 0x00000000 },
-   { 0x00000001, 0x20280061, 0x00000000, 0x0007000f },
-   { 0x00802001, 0x20200062, 0x00000000, 0xffffffff },
-   { 0x00802001, 0x20600062, 0x00000000, 0xffffffff },
-   { 0x00800031, 0x24001d28, 0x008d0020, 0x05502000 },
-   { 0x00000040, 0x20240c21, 0x00210024, 0x00000008 },
-   { 0x00800031, 0x24001d28, 0x008d0020, 0x05502000 },
+   { 0x00802001, 0x21000061, 0x00000000, 0xffffffff },
    { 0x00000001, 0x20280061, 0x00000000, 0x00070007 },
-   { 0x00802001, 0x20200062, 0x00000000, 0x80808080 },
-   { 0x00200008, 0x20201c21, 0x00450060, 0x00000001 },
+   { 0x00802001, 0x20200022, 0x008d0100, 0x00000000 },
+   { 0x00800031, 0x24001d28, 0x008d0020, 0x05302000 },
+   { 0x00000040, 0x20200c21, 0x00210060, 0x00000008 },
+   { 0x00800031, 0x24001d28, 0x008d0020, 0x05302000 },
+   { 0x00000040, 0x20240c21, 0x00210064, 0x00000008 },
+   { 0x00800031, 0x24001d28, 0x008d0020, 0x05302000 },
+   { 0x00000001, 0x20200021, 0x00210060, 0x00000000 },
+   { 0x00800031, 0x24001d28, 0x008d0020, 0x05302000 },
+   { 0x00802001, 0x20200062, 0x00000000, 0x7f7f7f7f },
+   { 0x00000008, 0x20201c21, 0x00210060, 0x00000001 },
+   { 0x00000008, 0x20241c21, 0x00210064, 0x00000001 },
    { 0x00800031, 0x24001d28, 0x008d0020, 0x05302002 },
    { 0x00800031, 0x24001d28, 0x008d0020, 0x05302001 },
    { 0x00800031, 0x24001d28, 0x008d0000, 0x87100000 },