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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-06-05 03:57:57 (GMT)
committerZhenyu Wang <zhenyuw@linux.intel.com>2009-06-10 02:24:51 (GMT)
commit4f40b33ef4b069b18a6a18406da83a23ca6e1127 (patch)
tree157371b99422bc1ed26e904fe978212b0e88e9b1
parentaccdbd23676d812d2345f86d8e3ee62f108841ff (diff)
Add new chipsets PCI ids
Desktop and mobile version of new chipsets are added. Also do memory config like Intel 4 series chipset. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
-rw-r--r--src/common.h27
-rw-r--r--src/i810_driver.c6
-rw-r--r--src/i830_driver.c14
3 files changed, 38 insertions, 9 deletions
diff --git a/src/common.h b/src/common.h
index 335fe75..69f5604 100644
--- a/src/common.h
+++ b/src/common.h
@@ -310,6 +310,16 @@ extern int I810_DEBUG;
#define PCI_CHIP_G41_G_BRIDGE 0x2E30
#endif
+#ifndef PCI_CHIP_IGDNG_D_G
+#define PCI_CHIP_IGDNG_D_G 0x0042
+#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040
+#endif
+
+#ifndef PCI_CHIP_IGDNG_M_G
+#define PCI_CHIP_IGDNG_M_G 0x0046
+#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044
+#endif
+
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
#define DEVICE_ID(p) (p)->device_id
@@ -339,7 +349,10 @@ extern int I810_DEBUG;
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810))
+#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
+#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
+#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
+#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810) || IS_IGDNG(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
@@ -347,20 +360,20 @@ extern int I810_DEBUG;
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810) || IS_G33CLASS(pI810))
#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810))
+#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
-#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810))
+#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* chipsets require graphics mem for hardware status page */
#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
(IS_G33CLASS(pI810) ||\
- IS_G4X(pI810)))
+ IS_G4X(pI810) || IS_IGDNG(pI810)))
/* chipsets require status page in non stolen memory */
-#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810))
-#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810))
+#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
+#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* dsparb controlled by hw only */
-#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810))
+#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
#define SUPPORTS_YTILING(pI810) (IS_I965G(pI830))
diff --git a/src/i810_driver.c b/src/i810_driver.c
index 21c35da..4b8c459 100644
--- a/src/i810_driver.c
+++ b/src/i810_driver.c
@@ -138,6 +138,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
{ 0, 0, 0 },
};
@@ -189,6 +191,8 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
{PCI_CHIP_G41_G, "G41"},
+ {PCI_CHIP_IGDNG_D_G, "IGDNG_D"},
+ {PCI_CHIP_IGDNG_M_G, "IGDNG_M"},
{-1, NULL}
};
@@ -225,6 +229,8 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{PCI_CHIP_G41_G, PCI_CHIP_G41_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 73d350f..8400872 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -118,6 +118,8 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
{PCI_CHIP_G41_G, "G41"},
+ {PCI_CHIP_IGDNG_D_G, "IGDNG_D"},
+ {PCI_CHIP_IGDNG_M_G, "IGDNG_M"},
{-1, NULL}
};
@@ -148,6 +150,8 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, RES_SHARED_VGA},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, RES_SHARED_VGA},
{PCI_CHIP_G41_G, PCI_CHIP_G41_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, RES_SHARED_VGA},
+ {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@@ -324,7 +328,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
/* new 4 series hardware has seperate GTT stolen with GFX stolen */
- if (IS_G4X(pI830) || IS_IGD(pI830))
+ if (IS_G4X(pI830) || IS_IGD(pI830) || IS_IGDNG(pI830))
range = 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
@@ -440,7 +444,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
- if (IS_G4X(pI830)) {
+ if (IS_G4X(pI830) || IS_IGDNG(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@@ -1135,6 +1139,12 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
case PCI_CHIP_G41_G:
chipname = "G41";
break;
+ case PCI_CHIP_IGDNG_D_G:
+ chipname = "IGDNG_D";
+ break;
+ case PCI_CHIP_IGDNG_M_G:
+ chipname = "IGDNG_M";
+ break;
default:
chipname = "unknown chipset";
break;