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authorEric Anholt <eric@anholt.net>2009-08-13 02:29:31 (GMT)
committer Eric Anholt <eric@anholt.net>2009-08-19 01:00:46 (GMT)
commit465a4ab416b2e5ad53b96702720331a44fffa2fe (patch) (side-by-side diff)
treeb0dd70cd7446e2117c057889fa6eb4aaa5f7f000
parenta3962e6f74ddd954ae1390d150a347745d7bdb24 (diff)
downloadxf86-video-intel-465a4ab416b2e5ad53b96702720331a44fffa2fe.zip
xf86-video-intel-465a4ab416b2e5ad53b96702720331a44fffa2fe.tar.gz
Align the height of untiled pixmaps to 2 lines as well.
The 965 docs note, and it's probably the case on 915 as well, that the 2x2 subspans are read as a unit, even if the bottom row isn't used. If the address in that bottom row extended beyond the end of the GTT, a fault could occur. Thanks to Chris Wilson for pointing out the problem.
Diffstat (more/less context) (ignore whitespace changes)
-rw-r--r--src/i830_uxa.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index bb1c616..af43a41 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -613,14 +613,17 @@ i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usag
pitch_align);
if (tiling == I915_TILING_NONE) {
- size = stride * h;
+ /* Round the height up so that the GPU's access to a 2x2 aligned
+ * subspan doesn't address an invalid page offset beyond the
+ * end of the GTT.
+ */
+ size = stride * ALIGN(h, 2);
} else {
int aligned_h = h;
if (tiling == I915_TILING_X)
aligned_h = ALIGN(h, 8);
else
aligned_h = ALIGN(h, 32);
- assert(aligned_h >= h);
stride = i830_get_fence_pitch(i830, stride, tiling);
/* Round the object up to the size of the fence it will live in