Include a chipset generation number to clarify device specific paths.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

13 files changed, 185 insertions, 162 deletions

diff --git a/src/i830_render.c b/src/i830_render.c
index 4bc582c9..52646d36 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -231,7 +231,7 @@ static uint32_t i8xx_get_card_format(intel_screen_private *intel,
 			return i830_tex_formats[i].card_fmt;
 	}
 
-	if (IS_I85X(intel) || IS_I865G(intel)) {
+	if (!(IS_I830(intel) || IS_845G(intel))) {
 		for (i = 0; i < sizeof(i855_tex_formats) / sizeof(i855_tex_formats[0]);
 		     i++) {
 			if (i855_tex_formats[i].fmt == picture->format)
diff --git a/src/i965_render.c b/src/i965_render.c
index 15fbe498..c0c5de4a 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -912,7 +912,7 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
 
 	wm_state->wm4.stats_enable = 1;	/* statistic */
 
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		wm_state->wm4.sampler_count = 0;	/* hardware requirement */
 	else
 		wm_state->wm4.sampler_count = 1;	/* 1-4 samplers used */
@@ -946,7 +946,7 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
 	/* binding table entry count is only used for prefetching, and it has to
 	 * be set 0 for IGDNG
 	 */
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		wm_state->thread1.binding_table_entry_count = 0;
 
 	drm_intel_bo_unmap(wm_state_bo);
@@ -977,7 +977,7 @@ static drm_intel_bo *gen4_create_vs_unit_state(ScrnInfoPtr scrn)
 	memset(&vs_state, 0, sizeof(vs_state));
 
 	/* Set up the vertex shader to be disabled (passthrough) */
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;	/* hardware requirement */
 	else
 		vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
@@ -1201,7 +1201,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 		OUT_BATCH(MI_FLUSH |
 			  MI_STATE_INSTRUCTION_CACHE_FLUSH |
 			  BRW_MI_GLOBAL_SNAPSHOT_RESET);
-		if (IS_G4X(intel) || IS_IGDNG(intel))
+		if (INTEL_INFO(intel)->gen >= 45)
 			OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 		else
 			OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -1213,7 +1213,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 		/* Zero out the two base address registers so all offsets are
 		 * absolute.
 		 */
-		if (IS_IGDNG(intel)) {
+		if (IS_GEN5(intel)) {
 			OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
 			OUT_BATCH(0 | BASE_ADDRESS_MODIFY);	/* Generate state base address */
 			OUT_BATCH(0 | BASE_ADDRESS_MODIFY);	/* Surface state base address */
@@ -1241,7 +1241,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 			  I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 	}
 
-	if (IS_IGDNG(intel)) {
+	if (IS_GEN5(intel)) {
 		/* Ironlake errata workaround: Before disabling the clipper,
 		 * you have to MI_FLUSH to get the pipeline idle.
 		 */
@@ -1252,7 +1252,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 		int pipe_ctrl;
 		/* Pipe control */
 
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			pipe_ctrl = BRW_PIPE_CONTROL_NOWRITE;
 		else
 			pipe_ctrl =
@@ -1369,7 +1369,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 			w_component = BRW_VFCOMPONENT_STORE_SRC;
 		}
 
-		if (IS_IGDNG(intel)) {
+		if (IS_GEN5(intel)) {
 			/*
 			 * The reason to add this extra vertex element in the header is that
 			 * IGDNG has different vertex header definition and origin method to
@@ -1412,7 +1412,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 			  (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
 			  (0 << VE0_OFFSET_SHIFT));
 
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
 				   VE1_VFCOMPONENT_0_SHIFT) |
 				  (BRW_VFCOMPONENT_STORE_SRC <<
@@ -1434,7 +1434,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 		/* u0, v0, w0 */
 		OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | ((2 * 4) << VE0_OFFSET_SHIFT));	/* offset vb in bytes */
 
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
 				   VE1_VFCOMPONENT_0_SHIFT) |
 				  (BRW_VFCOMPONENT_STORE_SRC <<
@@ -1448,7 +1448,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
 		if (mask) {
 			OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | (src_format << VE0_FORMAT_SHIFT) | (((2 + selem) * 4) << VE0_OFFSET_SHIFT));	/* vb offset in bytes */
 
-			if (IS_IGDNG(intel))
+			if (IS_GEN5(intel))
 				OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC <<
 					   VE1_VFCOMPONENT_0_SHIFT) |
 					  (BRW_VFCOMPONENT_STORE_SRC <<
@@ -1872,7 +1872,7 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
 	OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
 		  render_state->vb_offset * 4);
 
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
 			  render_state->vb_offset * 4 + i * 4);
 	else
@@ -1930,7 +1930,7 @@ void gen4_render_state_init(ScrnInfoPtr scrn)
 	render_state->vs_state_bo = gen4_create_vs_unit_state(scrn);
 
 	/* Set up the two SF states (one for blending with a mask, one without) */
-	if (IS_IGDNG(intel)) {
+	if (IS_GEN5(intel)) {
 		sf_kernel_bo = intel_bo_alloc_for_data(scrn,
 						       sf_kernel_static_gen5,
 						       sizeof
@@ -1958,7 +1958,7 @@ void gen4_render_state_init(ScrnInfoPtr scrn)
 	drm_intel_bo_unreference(sf_kernel_mask_bo);
 
 	for (m = 0; m < WM_KERNEL_COUNT; m++) {
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			render_state->wm_kernel_bo[m] =
 			    intel_bo_alloc_for_data(scrn,
 						    wm_kernels_gen5[m].data,
@@ -1989,7 +1989,7 @@ void gen4_render_state_init(ScrnInfoPtr scrn)
 								      border_color_bo);
 
 					for (m = 0; m < WM_KERNEL_COUNT; m++) {
-						if (IS_IGDNG(intel))
+						if (IS_GEN5(intel))
 							render_state->
 							    wm_state_bo[m][i][j]
 							    [k][l] =
diff --git a/src/i965_video.c b/src/i965_video.c
index c0cbd4b8..4ededde7 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -512,7 +512,7 @@ static drm_intel_bo *i965_create_vs_state(ScrnInfoPtr scrn)
 		return NULL;
 
 	/* Set up the vertex shader to be disabled (passthrough) */
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
 	else
 		vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
@@ -547,7 +547,7 @@ static drm_intel_bo *i965_create_sf_state(ScrnInfoPtr scrn)
 	drm_intel_bo *sf_bo, *kernel_bo;
 	struct brw_sf_unit_state *sf_state;
 
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		kernel_bo =
 		    i965_create_program(scrn, &sf_kernel_static_gen5[0][0],
 					sizeof(sf_kernel_static_gen5));
@@ -612,7 +612,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
 	struct brw_wm_unit_state *wm_state;
 
 	if (is_packed) {
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			kernel_bo =
 			    i965_create_program(scrn,
 						&ps_kernel_packed_static_gen5[0]
@@ -626,7 +626,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
 						sizeof
 						(ps_kernel_packed_static));
 	} else {
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			kernel_bo =
 			    i965_create_program(scrn,
 						&ps_kernel_planar_static_gen5[0]
@@ -664,7 +664,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
 	/* binding table entry count is only used for prefetching, and it has to
 	 * be set 0 for IGDNG
 	 */
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		wm_state->thread1.binding_table_entry_count = 0;
 
 	/* Though we never use the scratch space in our WM kernel, it has to be
@@ -682,7 +682,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
 	    intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, wm4),
 			     sampler_bo, 0,
 			     I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		wm_state->wm4.sampler_count = 0;
 	else
 		wm_state->wm4.sampler_count = 1;	/* 1-4 samplers used */
@@ -788,7 +788,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 
 	/* brw_debug (scrn, "before base address modify"); */
 	/* Match Mesa driver setup */
-	if (IS_G4X(intel) || IS_IGDNG(intel))
+	if (INTEL_INFO(intel)->gen >= 45)
 		OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 	else
 		OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@@ -801,7 +801,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 	/* Zero out the two base address registers so all offsets are
 	 * absolute
 	 */
-	if (IS_IGDNG(intel)) {
+	if (IS_GEN5(intel)) {
 		OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
 		OUT_BATCH(0 | BASE_ADDRESS_MODIFY);	/* Generate state base address */
 		OUT_BATCH(0 | BASE_ADDRESS_MODIFY);	/* Surface state base address */
@@ -832,7 +832,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 
 	/* brw_debug (scrn, "after base address modify"); */
 
-	if (IS_IGDNG(intel))
+	if (IS_GEN5(intel))
 		pipe_ctl = BRW_PIPE_CONTROL_NOWRITE;
 	else
 		pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
@@ -905,7 +905,7 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * bind_bo, int n_src_surf)
 
 	/* Set up our vertex elements, sourced from the single vertex buffer. */
 
-	if (IS_IGDNG(intel)) {
+	if (IS_GEN5(intel)) {
 		OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
 		/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
 		OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
@@ -1190,7 +1190,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
 
 		drm_intel_bo_unmap(vb_bo);
 
-		if (!IS_IGDNG(intel))
+		if (IS_GEN4(intel))
 			i965_pre_draw_debug(scrn);
 
 		/* If this command won't fit in the current batch, flush.
@@ -1212,7 +1212,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
 		OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
 			  VB0_VERTEXDATA | ((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
 		OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
-		if (IS_IGDNG(intel))
+		if (IS_GEN5(intel))
 			OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0,
 				  i * 4);
 		else
@@ -1232,7 +1232,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
 
 		drm_intel_bo_unreference(vb_bo);
 
-		if (!IS_IGDNG(intel))
+		if (IS_GEN4(intel))
 			i965_post_draw_debug(scrn);
 
 	}
diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
index a4802d0f..e7ca69da 100644
--- a/src/intel_batchbuffer.c
+++ b/src/intel_batchbuffer.c
@@ -148,7 +148,7 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn)
 
 	/* Big hammer, look to the pipelined flushes in future. */
 	flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
-	if (IS_I965G(intel))
+	if (INTEL_INFO(intel)->gen >= 40)
 		flags = 0;
 
 	BEGIN_BATCH(1);
@@ -194,7 +194,7 @@ void intel_batch_submit(ScrnInfoPtr scrn, int flush)
 		ret = dri_bo_exec(intel->batch_bo, intel->batch_used*4,
 				  NULL, 0, 0xffffffff);
 	if (ret != 0) {
-		if (ret == -EIO && !IS_I965G(intel)) {
+		if (ret == -EIO) {
 			static int once;
 
 			/* The GPU has hung and unlikely to recover by this point. */
diff --git a/src/intel_dri.c b/src/intel_dri.c
index 8c7a707f..7fd86554 100644
--- a/src/intel_dri.c
+++ b/src/intel_dri.c
@@ -456,20 +456,20 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion,
 			 * of extra time for the blitter to start up and
 			 * do its job for a full height blit
 			 */
-			if (full_height && !IS_I965G(intel))
+			if (full_height && INTEL_INFO(intel)->gen < 40)
 			    y2 -= 2;
 
 			if (pipe == 0) {
 				event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW;
 				load_scan_lines_pipe =
 				    MI_LOAD_SCAN_LINES_DISPLAY_PIPEA;
-				if (full_height && IS_I965G(intel))
+				if (full_height && INTEL_INFO(intel)->gen >= 40)
 				    event = MI_WAIT_FOR_PIPEA_SVBLANK;
 			} else {
 				event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW;
 				load_scan_lines_pipe =
 				    MI_LOAD_SCAN_LINES_DISPLAY_PIPEB;
-				if (full_height && IS_I965G(intel))
+				if (full_height && INTEL_INFO(intel)->gen >= 40)
 				    event = MI_WAIT_FOR_PIPEB_SVBLANK;
 			}
 
@@ -1174,7 +1174,7 @@ Bool I830DRI2ScreenInit(ScreenPtr screen)
 	intel->deviceName = drmGetDeviceNameFromFd(intel->drmSubFD);
 	memset(&info, '\0', sizeof(info));
 	info.fd = intel->drmSubFD;
-	info.driverName = IS_I965G(intel) ? "i965" : "i915";
+	info.driverName = IS_GEN3(intel) ? "i915" : "i965";
 	info.deviceName = intel->deviceName;
 
 #if DRI2INFOREC_VERSION == 1
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 50540dde..b16913b4 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -668,12 +668,10 @@ void IntelEmitInvarientState(ScrnInfoPtr scrn)
 	if (intel->last_3d != LAST_3D_OTHER)
 		return;
 
-	if (!IS_I965G(intel)) {
-		if (IS_I9XX(intel))
-			I915EmitInvarientState(scrn);
-		else
-			I830EmitInvarientState(scrn);
-	}
+	if (IS_GEN2(intel))
+		I830EmitInvarientState(scrn);
+	else if IS_GEN3(intel)
+		I915EmitInvarientState(scrn);
 }
 
 static void
@@ -816,7 +814,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv)
 	MessageType from;
 #endif
 	struct pci_device *const device = intel->PciInfo;
-	int fb_bar = IS_I9XX(intel) ? 2 : 0;
+	int fb_bar = IS_GEN2(intel) ? 0 : 2;
 
 	/*
 	 * The "VideoRam" config file parameter specifies the maximum amount of
@@ -872,7 +870,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv)
 
 	intel_batch_init(scrn);
 
-	if (IS_I965G(intel))
+	if (INTEL_INFO(intel)->gen >= 40)
 		gen4_render_state_init(scrn);
 
 	miClearVisualTypes();
@@ -972,7 +970,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr screen, int argc, char **argv)
 	xf86DPMSInit(screen, xf86DPMSSet, 0);
 
 #ifdef INTEL_XVMC
-	if (IS_I965G(intel))
+	if (INTEL_INFO(intel)->gen >= 40)
 		intel->XvMCEnabled = TRUE;
 	from = ((intel->directRenderingType == DRI_DRI2) &&
 		xf86GetOptValBool(intel->Options, OPTION_XVMC,
@@ -1115,10 +1113,7 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr screen)
 	}
 
 	if (intel->shadow_buffer) {
-		if (IS_I8XX(intel))
-			drm_intel_bo_unreference(intel->shadow_buffer);
-		else
-			free(intel->shadow_buffer);
+		free(intel->shadow_buffer);
 		intel->shadow_buffer = NULL;
 	}
 
@@ -1131,7 +1126,7 @@ static Bool I830CloseScreen(int scrnIndex, ScreenPtr screen)
 
 	intel_batch_teardown(scrn);
 
-	if (IS_I965G(intel))
+	if (INTEL_INFO(intel)->gen >= 40)
 		gen4_render_state_cleanup(scrn);
 
 	xf86_cursors_fini(screen);
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 31b30090..be8ec5f5 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -201,76 +201,38 @@
 #define SUBSYS_ID(p)      (p)->subdevice_id
 #define CHIP_REVISION(p)  (p)->revision
 
-#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 ||	\
-			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \
-			DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_E)
-#define IS_I815(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I815)
-#define IS_I830(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I830_M)
-#define IS_845G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_845_G)
-#define IS_I85X(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I854)
-#define IS_I852(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
-#define IS_I854(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I854)
-#define IS_I855(pI810)  (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
-#define IS_I865G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I865_G)
-#define IS_I8XX(pI810)	(IS_I830(pI810) || IS_845G(pI810) || IS_I85X(pI810) || IS_I865G(pI810))
+#define INTEL_INFO(intel) ((intel)->chipset.info)
+#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 10*(X) && INTEL_INFO(intel)->gen < 10*((X)+1))
+#define IS_GEN1(intel) IS_GENx(intel, 1)
+#define IS_GEN2(intel) IS_GENx(intel, 2)
+#define IS_GEN3(intel) IS_GENx(intel, 3)
+#define IS_GEN4(intel) IS_GENx(intel, 4)
+#define IS_GEN5(intel) IS_GENx(intel, 5)
+#define IS_GEN6(intel) IS_GENx(intel, 6)
+
+/* Some chips have specific errata (or limits) that we need to workaround. */
+#define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
+#define IS_845G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_845_G)
+#define IS_I865G(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I865_G)
 
 #define IS_I915G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_E7221_G)
 #define IS_I915GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I915_GM)
-#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
-#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
-#define IS_IGDGM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_G)
-#define IS_IGD(pI810) (IS_IGDG(pI810) || IS_IGDGM(pI810))
-#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
-#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_B43_G || IS_GM45(pI810))
-#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
+
 #define IS_965_Q(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q)
-#define IS_IGDNG_D(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_D_G)
-#define IS_IGDNG_M(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGDNG_M_G)
-#define IS_IGDNG(pI810) (IS_IGDNG_D(pI810) || IS_IGDNG_M(pI810))
-#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || \
-			 DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || \
-			 IS_G4X(pI810) || \
-			 IS_IGDNG(pI810) || \
-			 IS_GEN6(pI810))
-#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
- 			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
-			    DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G || \
-			    IS_IGD(pI810))
-
-#define IS_I9XX(pI810) (IS_I915G(pI810) ||			\
-			IS_I915GM(pI810) ||			\
-			IS_I945G(pI810) ||			\
-			IS_I945GM(pI810) ||			\
-			IS_I965G(pI810) ||			\
-			IS_G33CLASS(pI810))
-
-#define IS_I915(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_G33CLASS(pI810))
-
-#define IS_GEN6(pI810) ((pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_GT1 || \
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_GT2 || \
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT1 ||\
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS ||\
-			(pI810)->PciInfo->device_id == PCI_CHIP_SANDYBRIDGE_S_GT)
-
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_I965GM(pI810) || IS_GM45(pI810) || IS_IGD(pI810) || IS_IGDNG_M(pI810))
+
 /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
-#define SUPPORTS_YTILING(pI810) (IS_I965G(intel))
+#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
 
-#define ALWAYS_TILING(intel) (IS_GEN6(intel))
+#define ALWAYS_TILING(intel) IS_GEN6(intel)
 
 extern SymTabRec *intel_chipsets;
 
 struct intel_chipset {
     const char *name;
     int variant;
+    const struct intel_device_info {
+	    int gen;
+    } *info;
 };
 
 void intel_detect_chipset(ScrnInfoPtr scrn,
diff --git a/src/intel_hwmc.c b/src/intel_hwmc.c
index a0861ec8..d6267256 100644
--- a/src/intel_hwmc.c
+++ b/src/intel_hwmc.c
@@ -71,17 +71,17 @@ static int create_context(ScrnInfoPtr scrn, XvMCContextPtr pContext,
 
 	*num_priv = sizeof(struct intel_xvmc_hw_context) >> 2;
 
-	if (IS_I915(intel)) {
+	if (IS_GEN3(intel)) {
 		contextRec->type = XVMC_I915_MPEG2_MC;
 		contextRec->i915.use_phys_addr = 0;
 	} else {
-		if (IS_G4X(intel) || IS_IGDNG(intel))
+		if (INTEL_INFO(intel)->gen >= 45)
 			contextRec->type = XVMC_I965_MPEG2_VLD;
 		else
 			contextRec->type = XVMC_I965_MPEG2_MC;
-		contextRec->i965.is_g4x = IS_G4X(intel);
+		contextRec->i965.is_g4x = INTEL_INFO(intel)->gen == 45;
 		contextRec->i965.is_965_q = IS_965_Q(intel);
-		contextRec->i965.is_igdng = IS_IGDNG(intel);
+		contextRec->i965.is_igdng = IS_GEN5(intel);
 	}
 
 	return Success;
@@ -202,7 +202,7 @@ Bool intel_xvmc_adaptor_init(ScreenPtr pScreen)
 	if (IS_I915G(intel) || IS_I915GM(intel))
 		return FALSE;
 
-	if (!IS_I9XX(intel)) {
+	if (IS_GEN2(intel)) {
 		ErrorF("Your chipset doesn't support XvMC.\n");
 		return FALSE;
 	}
@@ -223,11 +223,11 @@ Bool intel_xvmc_adaptor_init(ScreenPtr pScreen)
 	pAdapt->CreateSubpicture =  create_subpicture;
 	pAdapt->DestroySubpicture = destroy_subpicture;
 
-	if (IS_I915(intel)) {
+	if (IS_GEN3(intel)) {
 		name = "i915_xvmc",
 		pAdapt->num_surfaces = ARRAY_SIZE(surface_info_i915);
 		pAdapt->surfaces = surface_info_i915;
-	} else if (IS_G4X(intel) || IS_IGDNG(intel)) {
+	} else if (INTEL_INFO(intel)->gen >= 45) {
 		name = "xvmc_vld",
 		pAdapt->num_surfaces = ARRAY_SIZE(surface_info_vld);
 		pAdapt->surfaces = surface_info_vld;
diff --git a/src/intel_memory.c b/src/intel_memory.c
index 3a25ba6a..f68db347 100644
--- a/src/intel_memory.c
+++ b/src/intel_memory.c
@@ -94,14 +94,14 @@ unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long si
 	unsigned long i;
 	unsigned long start;
 
-	if (IS_I965G(intel)) {
+	if (INTEL_INFO(intel)->gen >= 40) {
 		/* The 965 can have fences at any page boundary. */
 		return ALIGN(size, GTT_PAGE_SIZE);
 	} else {
 		/* Align the size to a power of two greater than the smallest fence
 		 * size.
 		 */
-		if (IS_I9XX(intel))
+		if (IS_GEN3(intel))
 			start = MB(1);
 		else
 			start = KB(512);
@@ -126,8 +126,8 @@ intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
 	if (tiling_mode == I915_TILING_NONE)
 		return pitch;
 
-	/* 965 is flexible */
-	if (IS_I965G(intel))
+	/* 965+ is flexible */
+	if (INTEL_INFO(intel)->gen >= 40)
 		return ALIGN(pitch, tile_width);
 
 	/* Pre-965 needs power of two tile width */
@@ -144,17 +144,16 @@ intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling)
 
 	/* 8xx spec has always 8K limit, but tests show larger limit in
 	   non-tiling mode, which makes large monitor work. */
-	if (IS_I8XX(intel) && tiling)
-		limit = KB(8);
-
-	if (IS_I915(intel) && tiling)
-		limit = KB(8);
-
-	if (IS_I965G(intel) && tiling)
-		limit = KB(16);
-
-	if (IS_IGDNG(intel) && tiling)
-		limit = KB(32);
+	if (tiling) {
+		if (IS_GEN2(intel))
+			limit = KB(8);
+		else if (IS_GEN3(intel))
+			limit = KB(8);
+		else if (IS_GEN4(intel))
+			limit = KB(16);
+		else
+			limit = KB(32);
+	}
 
 	if (stride <= limit)
 		return TRUE;
diff --git a/src/intel_module.c b/src/intel_module.c
index 8fd55edc..898e6973 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -39,6 +39,38 @@
 
 #include <xf86drmMode.h>
 
+static const struct intel_device_info intel_i81x_info = {
+	.gen = 10,
+};
+
+static const struct intel_device_info intel_i8xx_info = {
+	.gen = 20,
+};
+
+static const struct intel_device_info intel_i915_info = {
+	.gen = 30,
+};
+
+static const struct intel_device_info intel_g33_info = {
+	.gen = 33,
+};
+
+static const struct intel_device_info intel_i965_info = {
+	.gen = 40,
+};
+
+static const struct intel_device_info intel_g4x_info = {
+	.gen = 45,
+};
+
+static const struct intel_device_info intel_ironlake_info = {
+	.gen = 50,
+};
+
+static const struct intel_device_info intel_sandybridge_info = {
+	.gen = 60,
+};
+
 static const SymTabRec _intel_chipsets[] = {
     {PCI_CHIP_I810,		"i810"},
     {PCI_CHIP_I810_DC100,	"i810-dc100"},
@@ -188,24 +220,31 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
     switch (DEVICE_ID(pci)) {
     case PCI_CHIP_I810:
 	chipset->name = "i810";
+	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I810_DC100:
 	chipset->name = "i810-dc100";
+	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I810_E:
 	chipset->name = "i810e";
+	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I815:
 	chipset->name = "i815";
+	chipset->info = &intel_i81x_info;
 	break;
     case PCI_CHIP_I830_M:
 	chipset->name = "830M";
+	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_845_G:
 	chipset->name = "845G";
+	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I854:
 	chipset->name = "854";
+	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I855_GM:
 	/* Check capid register to find the chipset variant */
@@ -232,84 +271,111 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
 	    chipset->name = "852GM/855GM (unknown variant)";
 	    break;
 	}
+	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I865_G:
 	chipset->name = "865G";
+	chipset->info = &intel_i8xx_info;
 	break;
     case PCI_CHIP_I915_G:
 	chipset->name = "915G";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_E7221_G:
 	chipset->name = "E7221 (i915)";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I915_GM:
 	chipset->name = "915GM";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I945_G:
 	chipset->name = "945G";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I945_GM:
 	chipset->name = "945GM";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I945_GME:
 	chipset->name = "945GME";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_IGD_GM:
 	chipset->name = "Pineview GM";
+	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_IGD_G:
 	chipset->name = "Pineview G";
+	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_I965_G:
 	chipset->name = "965G";
+	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_G35_G:
 	chipset->name = "G35";
+	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_I965_Q:
 	chipset->name = "965Q";
+	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_I946_GZ:
 	chipset->name = "946GZ";
+	chipset->info = &intel_i915_info;
 	break;
     case PCI_CHIP_I965_GM:
 	chipset->name = "965GM";
+	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_I965_GME:
 	chipset->name = "965GME/GLE";
+	chipset->info = &intel_i965_info;
 	break;
     case PCI_CHIP_G33_G:
 	chipset->name = "G33";
+	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_Q35_G:
 	chipset->name = "Q35";
+	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_Q33_G:
 	chipset->name = "Q33";
+	chipset->info = &intel_g33_info;
 	break;
     case PCI_CHIP_GM45_GM:
 	chipset->name = "GM45";
+	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_IGD_E_G:
 	chipset->name = "4 Series";
+	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_G45_G:
 	chipset->name = "G45/G43";
+	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_Q45_G:
 	chipset->name = "Q45/Q43";
+	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_G41_G:
 	chipset->name = "G41";
+	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_B43_G:
 	chipset->name = "B43";
+	chipset->info = &intel_g4x_info;
 	break;
     case PCI_CHIP_IGDNG_D_G:
 	chipset->name = "Clarkdale";
+	chipset->info = &intel_ironlake_info;
 	break;
     case PCI_CHIP_IGDNG_M_G:
 	chipset->name = "Arrandale";
+	chipset->info = &intel_ironlake_info;
 	break;
     case PCI_CHIP_SANDYBRIDGE_GT1:
     case PCI_CHIP_SANDYBRIDGE_GT2:
@@ -319,6 +385,7 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
     case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
     case PCI_CHIP_SANDYBRIDGE_S_GT:
 	chipset->name = "Sandybridge";
+	chipset->info = &intel_sandybridge_info;
 	break;
     default:
 	chipset->name = "unknown chipset";
diff --git a/src/intel_shadow.c b/src/intel_shadow.c
index 37e4cd2d..c12febc4 100644
--- a/src/intel_shadow.c
+++ b/src/intel_shadow.c
@@ -108,7 +108,7 @@ void intel_shadow_blt(intel_screen_private *intel)
 	int n;
 
 	/* Can we trust the BLT? Otherwise do an uncached mmecy. */
-	if (IS_I8XX(intel) || IS_GEN6(intel)) {
+	if (IS_GEN2(intel) || IS_GEN6(intel)) {
 		intel_shadow_memcpy(intel);
 		return;
 	}
@@ -120,7 +120,7 @@ void intel_shadow_blt(intel_screen_private *intel)
 		blt |= (XY_SRC_COPY_BLT_WRITE_ALPHA |
 				XY_SRC_COPY_BLT_WRITE_RGB);
 
-	if (IS_I965G(intel)) {
+	if (INTEL_INFO(intel)->gen >= 40) {
 		if (intel->front_tiling) {
 			dst_pitch >>= 2;
 			blt |= XY_SRC_COPY_BLT_DST_TILED;
diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index fd7ca23c..23679bc8 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -96,7 +96,7 @@ ironlake_blt_workaround(ScrnInfoPtr scrn)
 	 * non-pipelined 3D instruction after each blit.
 	 */
 
-	if (IS_IGDNG(intel)) {
+	if (IS_GEN5(intel)) {
 		BEGIN_BATCH(2);
 		OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
 		OUT_BATCH(0);
@@ -144,7 +144,7 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
 		pitch = (w * pixmap->drawable.bitsPerPixel + 7) / 8;
 		pitch = ALIGN(pitch, 64);
 		size = pitch * ALIGN (h, 2);
-		if (!IS_I965G(intel)) {
+		if (INTEL_INFO(intel)->gen < 40) {
 			/* Older hardware requires fences to be pot size
 			 * aligned with a minimum of 1 MiB, so causes
 			 * massive overallocation for small textures.
@@ -302,7 +302,7 @@ static void i830_uxa_solid(PixmapPtr pixmap, int x1, int y1, int x2, int y2)
 			cmd |=
 			    XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
 
-		if (IS_I965G(intel) && intel_pixmap_tiled(pixmap)) {
+		if (INTEL_INFO(intel)->gen >= 40 && intel_pixmap_tiled(pixmap)) {
 			assert((pitch % 512) == 0);
 			pitch >>= 2;
 			cmd |= XY_COLOR_BLT_TILED;
@@ -457,7 +457,7 @@ i830_uxa_copy(PixmapPtr dest, int src_x1, int src_y1, int dst_x1,
 			    XY_SRC_COPY_BLT_WRITE_ALPHA |
 			    XY_SRC_COPY_BLT_WRITE_RGB;
 
-		if (IS_I965G(intel)) {
+		if (INTEL_INFO(intel)->gen >= 40) {
 			if (intel_pixmap_tiled(dest)) {
 				assert((dst_pitch % 512) == 0);
 				dst_pitch >>= 2;
@@ -1143,7 +1143,7 @@ intel_limits_init(intel_screen_private *intel)
 	 * the front, which will have an appropriate pitch/offset already set up,
 	 * so UXA doesn't need to worry.
 	 */
-	if (IS_I965G(intel)) {
+	if (INTEL_INFO(intel)->gen >= 40) {
 		intel->accel_pixmap_offset_alignment = 4 * 2;
 		intel->accel_max_x = 8192;
 		intel->accel_max_y = 8192;
@@ -1198,7 +1198,7 @@ Bool intel_uxa_init(ScreenPtr screen)
 	intel->uxa_driver->done_copy = i830_uxa_done_copy;
 
 	/* Composite */
-	if (!IS_I9XX(intel)) {
+	if (IS_GEN2(intel)) {
 		intel->uxa_driver->check_composite = i830_check_composite;
 		intel->uxa_driver->check_composite_target = i830_check_composite_target;
 		intel->uxa_driver->check_composite_texture = i830_check_composite_texture;
@@ -1207,8 +1207,7 @@ Bool intel_uxa_init(ScreenPtr screen)
 		intel->uxa_driver->done_composite = i830_done_composite;
 
 		intel->batch_flush_notify = i830_batch_flush_notify;
-	} else if (IS_I915G(intel) || IS_I915GM(intel) ||
-		   IS_I945G(intel) || IS_I945GM(intel) || IS_G33CLASS(intel)) {
+	} else if (IS_GEN3(intel)) {
 		intel->uxa_driver->check_composite = i915_check_composite;
 		intel->uxa_driver->check_composite_target = i915_check_composite_target;
 		intel->uxa_driver->check_composite_texture = i915_check_composite_texture;
diff --git a/src/intel_video.c b/src/intel_video.c
index a07120fa..5d167789 100644
--- a/src/intel_video.c
+++ b/src/intel_video.c
@@ -363,7 +363,8 @@ void I830InitVideo(ScreenPtr screen)
 	 * supported hardware.
 	 */
 	if (scrn->bitsPerPixel >= 16 &&
-	    (IS_I9XX(intel) || (IS_I965G(intel) && !IS_GEN6(intel))) &&
+	    INTEL_INFO(intel)->gen >= 30 &&
+	    INTEL_INFO(intel)->gen < 60 &&
 	    !intel->use_shadow) {
 		texturedAdaptor = I830SetupImageVideoTextured(screen);
 		if (texturedAdaptor != NULL) {
@@ -447,7 +448,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen)
 
 	adapt->pPortPrivates[0].ptr = (pointer) (adaptor_priv);
 	adapt->nAttributes = NUM_ATTRIBUTES;
-	if (IS_I9XX(intel))
+	if (INTEL_INFO(intel)->gen >= 30)
 		adapt->nAttributes += GAMMA_ATTRIBUTES;	/* has gamma */
 	adapt->pAttributes =
 	    xnfalloc(sizeof(XF86AttributeRec) * adapt->nAttributes);
@@ -456,7 +457,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen)
 	memcpy((char *)att, (char *)Attributes,
 	       sizeof(XF86AttributeRec) * NUM_ATTRIBUTES);
 	att += NUM_ATTRIBUTES;
-	if (IS_I9XX(intel)) {
+	if (INTEL_INFO(intel)->gen >= 30) {
 		memcpy((char *)att, (char *)GammaAttributes,
 		       sizeof(XF86AttributeRec) * GAMMA_ATTRIBUTES);
 		att += GAMMA_ATTRIBUTES;
@@ -507,7 +508,7 @@ static XF86VideoAdaptorPtr I830SetupImageVideoOverlay(ScreenPtr screen)
 	/* Allow the pipe to be switched from pipe A to B when in clone mode */
 	xvPipe = MAKE_ATOM("XV_PIPE");
 
-	if (IS_I9XX(intel)) {
+	if (INTEL_INFO(intel)->gen >= 30) {
 		xvGamma0 = MAKE_ATOM("XV_GAMMA0");
 		xvGamma1 = MAKE_ATOM("XV_GAMMA1");
 		xvGamma2 = MAKE_ATOM("XV_GAMMA2");
@@ -702,17 +703,17 @@ I830SetPortAttributeOverlay(ScrnInfoPtr scrn,
 			adaptor_priv->desired_crtc = NULL;
 		else
 			adaptor_priv->desired_crtc = xf86_config->crtc[value];
-	} else if (attribute == xvGamma0 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma0 && (INTEL_INFO(intel)->gen >= 30)) {
 		adaptor_priv->gamma0 = value;
-	} else if (attribute == xvGamma1 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma1 && (INTEL_INFO(intel)->gen >= 30)) {
 		adaptor_priv->gamma1 = value;
-	} else if (attribute == xvGamma2 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma2 && (INTEL_INFO(intel)->gen >= 30)) {
 		adaptor_priv->gamma2 = value;
-	} else if (attribute == xvGamma3 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma3 && (INTEL_INFO(intel)->gen >= 30)) {
 		adaptor_priv->gamma3 = value;
-	} else if (attribute == xvGamma4 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma4 && (INTEL_INFO(intel)->gen >= 30)) {
 		adaptor_priv->gamma4 = value;
-	} else if (attribute == xvGamma5 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma5 && (INTEL_INFO(intel)->gen >= 30)) {
 		adaptor_priv->gamma5 = value;
 	} else if (attribute == xvColorKey) {
 		adaptor_priv->colorKey = value;
@@ -725,7 +726,7 @@ I830SetPortAttributeOverlay(ScrnInfoPtr scrn,
 	     attribute == xvGamma2 ||
 	     attribute == xvGamma3 ||
 	     attribute == xvGamma4 ||
-	     attribute == xvGamma5) && (IS_I9XX(intel))) {
+	     attribute == xvGamma5) && (INTEL_INFO(intel)->gen >= 30)) {
 		OVERLAY_DEBUG("GAMMA\n");
 	}
 
@@ -759,17 +760,17 @@ I830GetPortAttribute(ScrnInfoPtr scrn,
 		if (c == xf86_config->num_crtc)
 			c = -1;
 		*value = c;
-	} else if (attribute == xvGamma0 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma0 && (INTEL_INFO(intel)->gen >= 30)) {
 		*value = adaptor_priv->gamma0;
-	} else if (attribute == xvGamma1 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma1 && (INTEL_INFO(intel)->gen >= 30)) {
 		*value = adaptor_priv->gamma1;
-	} else if (attribute == xvGamma2 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma2 && (INTEL_INFO(intel)->gen >= 30)) {
 		*value = adaptor_priv->gamma2;
-	} else if (attribute == xvGamma3 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma3 && (INTEL_INFO(intel)->gen >= 30)) {
 		*value = adaptor_priv->gamma3;
-	} else if (attribute == xvGamma4 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma4 && (INTEL_INFO(intel)->gen >= 30)) {
 		*value = adaptor_priv->gamma4;
-	} else if (attribute == xvGamma5 && (IS_I9XX(intel))) {
+	} else if (attribute == xvGamma5 && (INTEL_INFO(intel)->gen >= 30)) {
 		*value = adaptor_priv->gamma5;
 	} else if (attribute == xvColorKey) {
 		*value = adaptor_priv->colorKey;
@@ -1333,18 +1334,18 @@ intel_wait_for_scanline(ScrnInfoPtr scrn, PixmapPtr pixmap,
 	 * of extra time for the blitter to start up and
 	 * do its job for a full height blit
 	 */
-	if (full_height && !IS_I965G(intel))
+	if (full_height && INTEL_INFO(intel)->gen < 40)
 		y2 -= 2;
 
 	if (pipe == 0) {
 		pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEA;
 		event = MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW;
-		if (full_height && IS_I965G(intel))
+		if (full_height && INTEL_INFO(intel)->gen >= 40)
 			event = MI_WAIT_FOR_PIPEA_SVBLANK;
 	} else {
 		pipe = MI_LOAD_SCAN_LINES_DISPLAY_PIPEB;
 		event = MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW;
-		if (full_height && IS_I965G(intel))
+		if (full_height && INTEL_INFO(intel)->gen >= 40)
 			event = MI_WAIT_FOR_PIPEB_SVBLANK;
 	}
 
@@ -1401,7 +1402,7 @@ intel_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, sh
 	if (adaptor_priv->textured) {
 		pitchAlign = 4;
 	} else {
-		if (IS_I965G(intel))
+		if (INTEL_INFO(intel)->gen >= 40)
 			/* Actually the alignment is 64 bytes, too. But the
 			 * stride must be at least 512 bytes. Take the easy fix
 			 * and align on 512 bytes unconditionally. */
@@ -1417,7 +1418,7 @@ intel_setup_dst_params(ScrnInfoPtr scrn, intel_adaptor_private *adaptor_priv, sh
 
 #if INTEL_XVMC
 	/* for i915 xvmc, hw requires 1kb aligned surfaces */
-	if ((id == FOURCC_XVMC) && IS_I915(intel))
+	if ((id == FOURCC_XVMC) && IS_GEN3(intel))
 		pitchAlign = 1024;
 #endif
 
@@ -1582,7 +1583,7 @@ I830PutImageTextured(ScrnInfoPtr scrn,
 		intel_wait_for_scanline(scrn, pixmap, crtc, clipBoxes);
 	}
 
-	if (IS_I965G(intel)) {
+	if (INTEL_INFO(intel)->gen >= 40) {
 		I965DisplayVideoTextured(scrn, adaptor_priv, id, clipBoxes,
 					 width, height, dstPitch, dstPitch2,
 					 src_w, src_h,