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authorEric Anholt <eric@anholt.net>2008-12-29 10:41:02 -0800
committerEric Anholt <eric@anholt.net>2008-12-29 11:31:26 -0800
commit3544bbe22d8cf2640289e1e4febe755a47f26631 (patch)
tree20b7ec9fcdae65de361e9ef893eb2b39294a98a9
parent7b67914b23b54d4d9566190440a3430e40615aa8 (diff)
Add PCI write posting to LeaveVT path when we're about to wait on write results.
-rw-r--r--src/i830_driver.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 6fed32d9..90fa5070 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2339,6 +2339,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(DPLL_A_MD, pI830->saveDPLL_A_MD);
else
OUTREG(DPLL_A, pI830->saveDPLL_A);
+ POSTING_READ(DPLL_A);
i830_dpll_settle();
/* Restore mode config */
@@ -2362,6 +2363,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
}
OUTREG(PIPEACONF, pI830->savePIPEACONF);
+ POSTING_READ(PIPEACONF);
i830WaitForVblank(pScrn);
/*
@@ -2374,12 +2376,14 @@ RestoreHWState(ScrnInfoPtr pScrn)
DISPPLANE_SEL_PIPE_A) {
OUTREG(DSPACNTR, pI830->saveDSPACNTR);
OUTREG(DSPABASE, INREG(DSPABASE));
+ POSTING_READ(DSPABASE);
i830WaitForVblank(pScrn);
}
if ((pI830->saveDSPBCNTR & DISPPLANE_SEL_PIPE_MASK) ==
DISPPLANE_SEL_PIPE_A) {
OUTREG(DSPBCNTR, pI830->saveDSPBCNTR);
OUTREG(DSPBBASE, INREG(DSPBBASE));
+ POSTING_READ(DSPBBASE);
i830WaitForVblank(pScrn);
}
@@ -2403,6 +2407,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
OUTREG(DPLL_B_MD, pI830->saveDPLL_B_MD);
else
OUTREG(DPLL_B, pI830->saveDPLL_B);
+ POSTING_READ(DPLL_B);
i830_dpll_settle();
/* Restore mode config */
@@ -2425,6 +2430,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
}
OUTREG(PIPEBCONF, pI830->savePIPEBCONF);
+ POSTING_READ(PIPEBCONF);
i830WaitForVblank(pScrn);
/*