diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-03-23 17:28:22 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-03-24 16:37:41 +0000 |
| commit | 2eec53d0b9232970fe3d03ce6c8940ebeea44bee (patch) | |
| tree | ab489cc42216f5d2e7a6d9b6b1595800bb8767e4 | |
| parent | 9c037f61a490c96f9095f7ff3fecbf41f5efe9f7 (diff) | |
uxa: Default to using TILING_X for pixmaps.
On memory constrained hardware, tiling is vital for good performance as
it minimizes cache misses. The downside is that for older hardware
(which often suffers from the lack of bandwidth) requires the use of
fences for many operations, which are in short supply and so may cause
shorter batchbuffers. However our batch buffers are typically short and
so this is unlikely to be a concern and not affect the performance wins.
A quick bit of testing suggests the effect is inconclusive on
firefox/i945:
linear tiled
xcb 205.470 206.219
xcb-render-0.0 404.704 388.413
xlib 166.410 170.805
A secondary effect of the patch is to workaround a G31 specific hang
when attempting to use linear 2048x2048 surfaces. Bonus!
Fixes:
Bug 25375 - Performance issue using texture from pixmap (tfp) glx extension on 945
http://bugs.freedesktop.org/show_bug.cgi?id=25375
Bug 27100 - GPU Hung copying a 2048x1152 pixmap
http://bugs.freedesktop.org/show_bug.cgi?id=27100
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: John <jvinla@gmail.com>
| -rw-r--r-- | src/i830_uxa.c | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/src/i830_uxa.c b/src/i830_uxa.c index fec53782..22792fea 100644 --- a/src/i830_uxa.c +++ b/src/i830_uxa.c @@ -135,8 +135,20 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap, pitch_align = intel->accel_pixmap_pitch_alignment; size = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8, pitch_align) * ALIGN (h, 2); - if (size < 4096) + if (!IS_I965G(intel)) { + /* Older hardware requires fences to be pot size + * aligned with a minimum of 1 MiB, so causes + * massive overallocation for small textures. + */ + if (size < 1024*1024/2) + *tiling = I915_TILING_NONE; + } else if (size <= 4096) { + /* Disable tiling beneath a page size, we will not see + * any benefit from reducing TLB misses and instead + * just incur extra cost when we require a fence. + */ *tiling = I915_TILING_NONE; + } } repeat: @@ -863,11 +875,14 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth, return NullPixmap; } - if (usage == INTEL_CREATE_PIXMAP_TILING_X) - priv->tiling = I915_TILING_X; - else if (usage == INTEL_CREATE_PIXMAP_TILING_Y) + /* Always attempt to tile, compute_size() will remove the + * tiling for pixmaps that are either too large or too small + * to be effectively tiled. + */ + priv->tiling = I915_TILING_X; + if (usage == INTEL_CREATE_PIXMAP_TILING_Y) priv->tiling = I915_TILING_Y; - else + if (usage == UXA_CREATE_PIXMAP_FOR_MAP) priv->tiling = I915_TILING_NONE; size = i830_uxa_pixmap_compute_size(pixmap, w, h, |