diff options
| author | Keith Packard <keithp@keithp.com> | 2008-05-05 10:17:01 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2008-05-05 10:17:01 -0700 |
| commit | 0741020f3725c32c48ad15535b9c0549e4092c23 (patch) | |
| tree | bea37d464395ea0717bcd4bebd239abf96e81055 | |
| parent | 271abfd0ec29851273d8ca5241d963be5c64e43c (diff) | |
Set pin alignment for gem on non-965
non-965 tiled frame buffers have fairly strict alignment requirements, 512K
on 8xx and 1MB on 9xx, plus they must be aligned to the size of the
allocation.
| -rw-r--r-- | src/i830_memory.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/i830_memory.c b/src/i830_memory.c index cee46a87..550b4d85 100644 --- a/src/i830_memory.c +++ b/src/i830_memory.c @@ -171,6 +171,19 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem) int ret; pin.handle = mem->gem_handle; + pin.alignment = 0; + if (mem->tiling) { + if (IS_I965G(pI830)) + pin.alignment = 0; + else { + if (IS_I9XX (pI830)) + pin.alignment = 1024 * 1024; + else + pin.alignment = 512 * 1024; + if (pin.alignment < mem->size) + pin.alignment = mem->size; + } + } ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_PIN, &pin); if (ret != 0) return FALSE; |