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| author | Maciej Cencora <m.cencora@gmail.com> | 2008-08-07 06:53:39 -0700 |
|---|---|---|
| committer | Alex Deucher <alexdeucher@gmail.com> | 2008-08-25 06:30:47 -0400 |
| commit | c0170fef510b53a6ca2c6ea7a99119235229c929 (patch) | |
| tree | 39738466e1b5abcebff6b3ddc74f23359f5d8c90 | |
| parent | d9c38326cf70f57ab777ffdf9520b8cdea9d9cb6 (diff) | |
Add needed FP registers, etc. for r3xx bicubic Xv.
| -rw-r--r-- | src/radeon_reg.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 8b47dba4..ab08fec0 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -4530,6 +4530,7 @@ #define R300_US_TEX_INST_0 0x4620 #define R300_US_TEX_INST_1 0x4624 #define R300_US_TEX_INST_2 0x4628 +# define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4) # define R300_TEX_SRC_ADDR(x) (x << 0) # define R300_TEX_DST_ADDR(x) (x << 6) # define R300_TEX_ID(x) (x << 11) @@ -4542,11 +4543,13 @@ #define R300_US_ALU_RGB_ADDR_0 0x46c0 #define R300_US_ALU_RGB_ADDR_1 0x46c4 #define R300_US_ALU_RGB_ADDR_2 0x46c8 +# define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4) /* for ADDR0-2, values 0-31 specify a location in the pixel stack, values 32-63 specify a constant */ # define R300_ALU_RGB_ADDR0(x) (x << 0) # define R300_ALU_RGB_ADDR1(x) (x << 6) # define R300_ALU_RGB_ADDR2(x) (x << 12) +# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5)) /* ADDRD - where on the pixel stack the result of this instruction will be written */ # define R300_ALU_RGB_ADDRD(x) (x << 18) @@ -4556,6 +4559,7 @@ # define R300_ALU_RGB_MASK_R 1 # define R300_ALU_RGB_MASK_G 2 # define R300_ALU_RGB_MASK_B 4 +# define R300_ALU_RGB_MASK_RGB 7 # define R300_ALU_RGB_TARGET_A (0 << 29) # define R300_ALU_RGB_TARGET_B (1 << 29) # define R300_ALU_RGB_TARGET_C (2 << 29) @@ -4563,6 +4567,7 @@ #define R300_US_ALU_RGB_INST_0 0x48c0 #define R300_US_ALU_RGB_INST_1 0x48c4 #define R300_US_ALU_RGB_INST_2 0x48c8 +# define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4) # define R300_ALU_RGB_SEL_A(x) (x << 0) # define R300_ALU_RGB_SRC0_RGB 0 # define R300_ALU_RGB_SRC0_RRR 1 @@ -4634,11 +4639,13 @@ #define R300_US_ALU_ALPHA_ADDR_0 0x47c0 #define R300_US_ALU_ALPHA_ADDR_1 0x47c4 #define R300_US_ALU_ALPHA_ADDR_2 0x47c8 +# define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4) /* for ADDR0-2, values 0-31 specify a location in the pixel stack, values 32-63 specify a constant */ # define R300_ALU_ALPHA_ADDR0(x) (x << 0) # define R300_ALU_ALPHA_ADDR1(x) (x << 6) # define R300_ALU_ALPHA_ADDR2(x) (x << 12) +# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5)) /* ADDRD - where on the pixel stack the result of this instruction will be written */ # define R300_ALU_ALPHA_ADDRD(x) (x << 18) @@ -4654,6 +4661,7 @@ #define R300_US_ALU_ALPHA_INST_0 0x49c0 #define R300_US_ALU_ALPHA_INST_1 0x49c4 #define R300_US_ALU_ALPHA_INST_2 0x49c8 +# define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4) # define R300_ALU_ALPHA_SEL_A(x) (x << 0) # define R300_ALU_ALPHA_SRC0_R 0 # define R300_ALU_ALPHA_SRC0_G 1 @@ -4710,6 +4718,15 @@ # define R300_ALU_ALPHA_OMOD_DIV_8 6 # define R300_ALU_ALPHA_CLAMP (1 << 30) +#define R300_US_ALU_CONST_R_0 0x4c00 +# define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16) +#define R300_US_ALU_CONST_G_0 0x4c04 +# define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16) +#define R300_US_ALU_CONST_B_0 0x4c08 +# define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16) +#define R300_US_ALU_CONST_A_0 0x4c0c +# define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16) + #define R300_FG_DEPTH_SRC 0x4bd8 #define R300_FG_FOG_BLEND 0x4bc0 #define R300_FG_ALPHA_FUNC 0x4bd4 |