r600: fixup problems with EXA operation reset for multiple ops

To put multiple ops into one CS, you can't just discard the whole
IB. This add supports for reset the CS cdw to the correct place
after an op discards.

Still doesn't enable the final accel bits.

5 files changed, 30 insertions, 23 deletions

diff --git a/src/r600_exa.c b/src/r600_exa.c
index 34880704..1405db78 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -220,10 +220,6 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     r600_cp_start(pScrn);
 
     /* Init */
-#if defined(XF86DRM_MODE)
-    if (info->cs)
-	accel_state->XInited3D = FALSE;
-#endif
     start_3d(pScrn, accel_state->ib);
 
     set_default_state(pScrn, accel_state->ib);
@@ -454,9 +450,7 @@ R600DoneSolid(PixmapPtr pPix)
 			accel_state->dst_size, accel_state->dst_mc_addr,
 			accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 
-    accel_state->vb_start_op = 0;
-
-    R600CPFlushIndirect(pScrn, accel_state->ib);
+    r600_finish_op(pScrn);
 }
 
 static void
@@ -500,10 +494,6 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn,
     r600_cp_start(pScrn);
 
     /* Init */
-#if defined(XF86DRM_MODE)
-    if (info->cs)
-	accel_state->XInited3D = FALSE;
-#endif
     start_3d(pScrn, accel_state->ib);
 
     set_default_state(pScrn, accel_state->ib);
@@ -720,8 +710,7 @@ R600DoCopy(ScrnInfoPtr pScrn)
 			accel_state->dst_size, accel_state->dst_mc_addr,
 			accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 
-    accel_state->vb_start_op = 0;
-    R600CPFlushIndirect(pScrn, accel_state->ib);
+    r600_finish_op(pScrn);
 }
 
 static void
@@ -858,7 +847,6 @@ R600PrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
 						       RADEON_GEM_DOMAIN_VRAM,
 						       0);
 	    if (accel_state->copy_area_bo == NULL) {
-		R600IBDiscard(pScrn, accel_state->ib);
 		return FALSE;
 	    }
 	    radeon_cs_space_add_persistent_bo(info->cs, accel_state->copy_area_bo,
@@ -866,7 +854,6 @@ R600PrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
 	    if (radeon_cs_space_check(info->cs)) {
 		radeon_bo_unref(accel_state->copy_area_bo);
 		accel_state->copy_area_bo = NULL;
-		R600IBDiscard(pScrn, accel_state->ib);
 		return FALSE;
 	    }
 	    accel_state->copy_area = (void*)accel_state->copy_area_bo;
@@ -1733,10 +1720,6 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
     r600_cp_start(pScrn);
 
     /* Init */
-#if defined(XF86DRM_MODE)
-    if (info->cs)
-	accel_state->XInited3D = FALSE;
-#endif
     start_3d(pScrn, accel_state->ib);
 
     set_default_state(pScrn, accel_state->ib);
@@ -2049,8 +2032,7 @@ static void R600DoneComposite(PixmapPtr pDst)
 			accel_state->dst_size, accel_state->dst_mc_addr,
 			accel_state->dst_bo, RADEON_GEM_DOMAIN_VRAM, 0);
 
-    accel_state->vb_start_op = 0;
-    R600CPFlushIndirect(pScrn, accel_state->ib);
+    r600_finish_op(pScrn);
 }
 
 Bool
diff --git a/src/r600_state.h b/src/r600_state.h
index 46c18f9d..b2d2433a 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -326,6 +326,8 @@ void
 r600_vb_discard(ScrnInfoPtr pScrn);
 int
 r600_cp_start(ScrnInfoPtr pScrn);
+void
+r600_finish_op(ScrnInfoPtr pScrn);
 
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index c740e066..0318e603 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -112,8 +112,7 @@ R600DoneTexturedVideo(ScrnInfoPtr pScrn)
 			accel_state->dst_size, accel_state->dst_mc_addr,
 			accel_state->dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
 
-    accel_state->vb_start_op = 0;
-    R600CPFlushIndirect(pScrn, accel_state->ib);
+    r600_finish_op(pScrn);
 }
 
 void
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index 50afaed6..0ca44adb 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -83,6 +83,12 @@ void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib)
     int ret;
     RADEONInfoPtr info = RADEONPTR(pScrn);
     if (info->cs) {
+	if (info->accel_state->ib_reset_op) {
+	    /* if we have data just reset the CS and ignore the operation */
+	    info->cs->cdw = info->accel_state->ib_reset_op;
+	    info->accel_state->ib_reset_op = 0;
+	    return;
+	}
 	if (info->accel_state->vb_ptr) {
 	    radeon_bo_unmap(info->accel_state->vb_bo);
 	    info->accel_state->vb_ptr = NULL;
@@ -1203,6 +1209,10 @@ r600_cp_start(ScrnInfoPtr pScrn)
 
 #if defined(XF86DRM_MODE)
     if (info->cs) {
+
+	if (CS_FULL(info->cs)) {
+	    radeon_cs_flush_indirect(pScrn);
+	}
 	if (!r600_vb_get(pScrn))
 	    return -1;
 	if (accel_state->vb_bo)
@@ -1210,6 +1220,7 @@ r600_cp_start(ScrnInfoPtr pScrn)
 					    RADEON_GEM_DOMAIN_GTT, 0);
 
 	radeon_cs_space_check(info->cs);
+	accel_state->ib_reset_op = info->cs->cdw;
     } else
 #endif
     {
@@ -1220,3 +1231,14 @@ r600_cp_start(ScrnInfoPtr pScrn)
     }
     return 0;
 }
+
+void r600_finish_op(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    struct radeon_accel_state *accel_state = info->accel_state;
+    
+    accel_state->vb_start_op = 0;
+    accel_state->ib_reset_op = 0;
+
+    R600CPFlushIndirect(pScrn, accel_state->ib);
+}
diff --git a/src/radeon.h b/src/radeon.h
index 745ee8e5..4ee37b51 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -710,6 +710,8 @@ struct radeon_accel_state {
     uint32_t          vb_size;
     struct radeon_bo  *vb_bo;
     uint32_t          vb_start_op;
+    /* where to discard IB from if we cancel operation */
+    uint32_t          ib_reset_op;
 
     // shader storage
     ExaOffscreenArea  *shaders;