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authorDave Airlie <airlied@redhat.com>2011-12-05 18:44:28 +0000
committerDave Airlie <airlied@redhat.com>2011-12-05 18:44:28 +0000
commit98b2d5fe1722a43c4bbe7711ed7180a3fb65305f (patch)
treea2b1fb23519cfdd7d6555225c3142e273806fcf4
parent7dcefc69d9fbceae27cd03083c815e01a19b527e (diff)
radeon: r200 depth buffers are always tiled
When we do the allocations we need to make sure the always tiled nature is taken into account. Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--src/radeon.h1
-rw-r--r--src/radeon_dri2.c8
-rw-r--r--src/radeon_exa.c3
3 files changed, 12 insertions, 0 deletions
diff --git a/src/radeon.h b/src/radeon.h
index 34f6f53e..91c7b624 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1667,6 +1667,7 @@ static __inline__ int radeon_timedout(const struct timeval *endtime)
enum {
RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000,
RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000,
+ RADEON_CREATE_PIXMAP_DEPTH = 0x40000000, /* for r200 */
};
#endif /* _RADEON_H_ */
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 8789d735..9fd3658f 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -121,6 +121,8 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferDepthStencil:
if (info->ChipFamily >= CHIP_FAMILY_R600) {
@@ -132,6 +134,8 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
need_enlarge = 1;
} else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
@@ -271,6 +275,8 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferDepthStencil:
/* macro is the preferred setting, but the 2D detiling for software
@@ -282,6 +288,8 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
need_enlarge = 1;
} else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | RADEON_CREATE_PIXMAP_TILING_MICRO;
+ if (IS_R200_3D)
+ flags |= RADEON_CREATE_PIXMAP_DEPTH;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index f3daec04..95646ab1 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -473,6 +473,9 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MICRO)
tiling |= RADEON_TILING_MICRO;
}
+ if ((usage_hint & RADEON_CREATE_PIXMAP_DEPTH) && IS_R200_3D)
+ tiling |= RADEON_TILING_MACRO | RADEON_TILING_MICRO;
+
}
/* Small pixmaps must not be macrotiled on R300, hw cannot sample them