kms: EXA/Xv tiling fixes

- properly set tiling flags for temp surfaces
- fix CB non_disp_tiling bits on evergreen

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>

5 files changed, 28 insertions, 6 deletions

diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index d41ce722..12626c32 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -148,7 +148,7 @@ evergreen_sq_setup(ScrnInfoPtr pScrn, sq_config_t *sq_conf)
 void
 evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain)
 {
-    uint32_t cb_color_info, cb_color_attrib, cb_color_dim;
+    uint32_t cb_color_info, cb_color_attrib = 0, cb_color_dim;
     int pitch, slice, h;
     RADEONInfoPtr info = RADEONPTR(pScrn);
 
@@ -177,7 +177,8 @@ evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t do
 	cb_color_info |= RAT_bit;
 
     /* bit 4 needs to be set for linear and depth/stencil surfaces */
-    cb_color_attrib = CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit;
+    if (cb_conf->non_disp_tiling)
+	cb_color_attrib |= CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit;
 
     pitch = (cb_conf->w / 8) - 1;
     h = RADEON_ALIGN(cb_conf->h, 8);
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index d4511544..e5e75593 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -149,8 +149,10 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
     if (accel_state->planemask & 0xff000000)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
-    if (accel_state->dst_obj.tiling_flags == 0)
+    if (accel_state->dst_obj.tiling_flags == 0) {
 	cb_conf.array_mode = 1;
+	cb_conf.non_disp_tiling = 1;
+    }
     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
 
     evergreen_set_spi(pScrn, 0, 0);
@@ -354,8 +356,10 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
     if (accel_state->planemask & 0xff000000)
 	cb_conf.pmask |= 8; /* A */
     cb_conf.rop = accel_state->rop;
-    if (accel_state->dst_obj.tiling_flags == 0)
+    if (accel_state->dst_obj.tiling_flags == 0) {
 	cb_conf.array_mode = 1;
+	cb_conf.non_disp_tiling = 1;
+    }
     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
 
     evergreen_set_spi(pScrn, (1 - 1), 1);
@@ -515,12 +519,15 @@ EVERGREENCopy(PixmapPtr pDst,
     if (accel_state->same_surface && accel_state->copy_area) {
 	uint32_t orig_dst_domain = accel_state->dst_obj.domain;
 	uint32_t orig_src_domain = accel_state->src_obj[0].domain;
+	uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
+	uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
 	struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
 
 	/* src to tmp */
 	accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
 	accel_state->dst_obj.bo = accel_state->copy_area_bo;
 	accel_state->dst_obj.offset = 0;
+	accel_state->dst_obj.tiling_flags = 0;
 	EVERGREENDoPrepareCopy(pScrn);
 	EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
 	EVERGREENDoCopy(pScrn);
@@ -529,9 +536,11 @@ EVERGREENCopy(PixmapPtr pDst,
 	accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
 	accel_state->src_obj[0].bo = accel_state->copy_area_bo;
 	accel_state->src_obj[0].offset = 0;
+	accel_state->src_obj[0].tiling_flags = 0;
 	accel_state->dst_obj.domain = orig_dst_domain;
 	accel_state->dst_obj.bo = orig_bo;
 	accel_state->dst_obj.offset = 0;
+	accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
 	EVERGREENDoPrepareCopy(pScrn);
 	EVERGREENAppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h);
 	EVERGREENDoCopyVline(pDst);
@@ -540,6 +549,7 @@ EVERGREENCopy(PixmapPtr pDst,
 	accel_state->src_obj[0].domain = orig_src_domain;
 	accel_state->src_obj[0].bo = orig_bo;
 	accel_state->src_obj[0].offset = 0;
+	accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
     } else
 	EVERGREENAppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
 
@@ -1241,8 +1251,10 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
     cb_conf.blendcntl |= CB_BLEND0_CONTROL__ENABLE_bit;
     cb_conf.rop = 3;
     cb_conf.pmask = 0xf;
-    if (accel_state->dst_obj.tiling_flags == 0)
+    if (accel_state->dst_obj.tiling_flags == 0) {
 	cb_conf.array_mode = 1;
+	cb_conf.non_disp_tiling = 1;
+    }
 #if X_BYTE_ORDER == X_BIG_ENDIAN
     switch (dst_obj.bpp) {
     case 16:
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 1c154df3..480c1411 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -71,6 +71,7 @@ typedef struct {
     int format;
     int endian;
     int array_mode;						// tiling
+    int non_disp_tiling;
     int number_type;
     int read_size;
     int comp_swap;
diff --git a/src/evergreen_textured_videofuncs.c b/src/evergreen_textured_videofuncs.c
index 315e2bac..147cd4e0 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -441,8 +441,10 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
     cb_conf.blend_clamp = 1;
     cb_conf.pmask = 0xf;
     cb_conf.rop = 3;
-    if (accel_state->dst_obj.tiling_flags == 0)
+    if (accel_state->dst_obj.tiling_flags == 0) {
 	cb_conf.array_mode = 1;
+	cb_conf.non_disp_tiling = 1;
+    }
     evergreen_set_render_target(pScrn, &cb_conf, accel_state->dst_obj.domain);
 
     evergreen_set_spi(pScrn, (1 - 1), 1);
diff --git a/src/r600_exa.c b/src/r600_exa.c
index ea584827..ab5e33b7 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -684,6 +684,8 @@ R600Copy(PixmapPtr pDst,
 	uint32_t orig_offset, tmp_offset;
 	uint32_t orig_dst_domain = accel_state->dst_obj.domain;
 	uint32_t orig_src_domain = accel_state->src_obj[0].domain;
+	uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
+	uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
 	struct radeon_bo *orig_bo = accel_state->dst_obj.bo;
 
 #if defined(XF86DRM_MODE)
@@ -701,6 +703,7 @@ R600Copy(PixmapPtr pDst,
 	accel_state->dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
 	accel_state->dst_obj.bo = accel_state->copy_area_bo;
 	accel_state->dst_obj.offset = tmp_offset;
+	accel_state->dst_obj.tiling_flags = 0;
 	R600DoPrepareCopy(pScrn);
 	R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);
 	R600DoCopy(pScrn);
@@ -709,9 +712,11 @@ R600Copy(PixmapPtr pDst,
 	accel_state->src_obj[0].domain = RADEON_GEM_DOMAIN_VRAM;
 	accel_state->src_obj[0].bo = accel_state->copy_area_bo;
 	accel_state->src_obj[0].offset = tmp_offset;
+	accel_state->src_obj[0].tiling_flags = 0;
 	accel_state->dst_obj.domain = orig_dst_domain;
 	accel_state->dst_obj.bo = orig_bo;
 	accel_state->dst_obj.offset = orig_offset;
+	accel_state->dst_obj.tiling_flags = orig_dst_tiling_flags;
 	R600DoPrepareCopy(pScrn);
 	R600AppendCopyVertex(pScrn, dstX, dstY, dstX, dstY, w, h);
 	R600DoCopyVline(pDst);
@@ -720,6 +725,7 @@ R600Copy(PixmapPtr pDst,
 	accel_state->src_obj[0].domain = orig_src_domain;
 	accel_state->src_obj[0].bo = orig_bo;
 	accel_state->src_obj[0].offset = orig_offset;
+	accel_state->src_obj[0].tiling_flags = orig_src_tiling_flags;
     } else
 	R600AppendCopyVertex(pScrn, srcX, srcY, dstX, dstY, w, h);