drm/radeon: unify fb bo alignment harder

More duplicated paths discoved...

3 files changed, 32 insertions, 25 deletions

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 9644e734..3939ddfc 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -426,10 +426,10 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height)
 	int ret;
 	unsigned long rotate_pitch;
 
-	width = RADEON_ALIGN(width, 64);
-	rotate_pitch = width * drmmode->cpp;
-
-	size = rotate_pitch * height;
+	rotate_pitch =
+		RADEON_ALIGN(width * drmmode->cpp, drmmode_get_pitch_align(crtc->scrn, drmmode->cpp, 0));
+	height = RADEON_ALIGN(height, drmmode_get_height_align(crtc->scrn, 0));
+	size = RADEON_ALIGN(rotate_pitch * height, RADEON_GPU_PAGE_SIZE);
 
 	rotate_bo = radeon_bo_open(drmmode->bufmgr, 0, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 	if (rotate_bo == NULL)
@@ -1133,15 +1133,13 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 			tiling_flags |= RADEON_TILING_MACRO;
 	}
 
-	pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags) / cpp);
+	pitch = RADEON_ALIGN(width * cpp, drmmode_get_pitch_align(scrn, cpp, tiling_flags));
 	height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags));
-
-	screen_size = pitch * height * cpp;
-	screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
+	screen_size = RADEON_ALIGN(pitch * height, RADEON_GPU_PAGE_SIZE);
 
 	xf86DrvMsg(scrn->scrnIndex, X_INFO,
 		   "Allocate new frame buffer %dx%d stride %d\n",
-		   width, height, pitch);
+		   width, height, pitch / cpp);
 
 	old_width = scrn->virtualX;
 	old_height = scrn->virtualY;
@@ -1151,7 +1149,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 
 	scrn->virtualX = width;
 	scrn->virtualY = height;
-	scrn->displayWidth = pitch;
+	scrn->displayWidth = pitch / cpp;
 
 	info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 	if (!info->front_bo)
@@ -1169,10 +1167,10 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 #endif
 	if (tiling_flags)
 	    radeon_bo_set_tiling(info->front_bo,
-				 tiling_flags | RADEON_TILING_SURFACE, pitch * cpp);
+				 tiling_flags | RADEON_TILING_SURFACE, pitch);
 
 	ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth,
-			   scrn->bitsPerPixel, pitch * cpp,
+			   scrn->bitsPerPixel, pitch,
 			   info->front_bo->handle,
 			   &drmmode->fb_id);
 	if (ret)
@@ -1181,7 +1179,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 	if (!info->r600_shadow_fb) {
 		radeon_set_pixmap_bo(ppix, info->front_bo);
 		screen->ModifyPixmapHeader(ppix,
-					   width, height, -1, -1, pitch * cpp, NULL);
+					   width, height, -1, -1, pitch, NULL);
 	} else {
 		if (radeon_bo_map(info->front_bo, 1))
 			goto fail;
@@ -1191,7 +1189,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 		free(info->fb_shadow);
 		info->fb_shadow = fb_shadow;
 		screen->ModifyPixmapHeader(ppix,
-					   width, height, -1, -1, pitch * cpp,
+					   width, height, -1, -1, pitch,
 					   info->fb_shadow);
 	}
 #if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,9,99,1,0)
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 99ad8437..b62ff592 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -429,7 +429,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
     ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_exa_pixmap_priv *new_priv;
-    int padded_width;
+    int pitch;
     uint32_t size;
     uint32_t tiling = 0;
     int cpp = bitsPerPixel / 8;
@@ -462,10 +462,8 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
     }
 
     height = RADEON_ALIGN(height, drmmode_get_height_align(pScrn, tiling));
-    padded_width = ((width * bitsPerPixel + FB_MASK) >> FB_SHIFT) * sizeof(FbBits);
-    padded_width = RADEON_ALIGN(padded_width, drmmode_get_pitch_align(pScrn, cpp, tiling));
-    size = height * padded_width;
-    size = RADEON_ALIGN(size, RADEON_GPU_PAGE_SIZE);
+    pitch = RADEON_ALIGN(width * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling));
+    size = RADEON_ALIGN(height * pitch, RADEON_GPU_PAGE_SIZE);
 
     new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
     if (!new_priv)
@@ -474,7 +472,7 @@ void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
     if (size == 0)
 	return new_priv;
 
-    *new_pitch = padded_width;
+    *new_pitch = pitch;
 
     new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, 0,
 				  RADEON_GEM_DOMAIN_VRAM, 0);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index e2406075..642e4917 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -528,6 +528,8 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
     DevUnion* pPriv;
     Gamma  zeros = { 0.0, 0.0, 0.0 };
     Bool colorTilingDefault;
+    uint32_t tiling = 0;
+    int cpp;
 
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONPreInit_KMS\n");
@@ -671,7 +673,16 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
     else
     	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 		"EXA: Driver will not allow EXA pixmaps in VRAM\n");
-    RADEONSetPitch(pScrn);
+
+    /* no tiled scanout on r6xx+ yet */
+    if (info->allowColorTiling) {
+	if (info->ChipFamily < CHIP_FAMILY_R600)
+	    tiling |= RADEON_TILING_MACRO;
+    }
+    cpp = pScrn->bitsPerPixel / 8;
+    pScrn->displayWidth =
+	RADEON_ALIGN(pScrn->virtualX * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling)) / cpp;
+    info->CurrentLayout.displayWidth = pScrn->displayWidth;
 
     /* Set display resolution */
     xf86SetDpi(pScrn, 0, 0);
@@ -1088,7 +1099,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
     xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
     int cpp = info->CurrentLayout.pixel_bytes;
     int screen_size;
-    int stride;
+    int pitch;
     int total_size_bytes = 0, remain_size_bytes;
     uint32_t tiling_flags = 0;
 
@@ -1107,8 +1118,8 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
 	if (info->ChipFamily < CHIP_FAMILY_R600)
 	    tiling_flags |= RADEON_TILING_MACRO;
     }
-    stride = RADEON_ALIGN(pScrn->displayWidth * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling_flags));
-    screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * stride;
+    pitch = RADEON_ALIGN(pScrn->displayWidth * cpp, drmmode_get_pitch_align(pScrn, cpp, tiling_flags));
+    screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
     {
 	int cursor_size = 64 * 4 * 64;
 	int c;
@@ -1168,7 +1179,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
 #endif
 	if (tiling_flags) {
             radeon_bo_set_tiling(info->front_bo,
-				 tiling_flags | RADEON_TILING_SURFACE, stride);
+				 tiling_flags | RADEON_TILING_SURFACE, pitch);
 	}
     }