diff options
| -rw-r--r-- | src/nv_bios.c | 6 | ||||
| -rw-r--r-- | src/nv_setup.c | 2 | ||||
| -rw-r--r-- | src/nvreg.h | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/nv_bios.c b/src/nv_bios.c index dd9aa0e..0b67961 100644 --- a/src/nv_bios.c +++ b/src/nv_bios.c @@ -1778,7 +1778,7 @@ static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, i * * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so * that the hardware can correctly calculate how much VRAM it has - * (and subsequently report that value in 0x10020C) + * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C)) * * The implementation of this opcode in general consists of two parts: * 1) determination of the memory bus width @@ -1789,8 +1789,8 @@ static bool init_compute_mem(ScrnInfoPtr pScrn, bios_t *bios, uint16_t offset, i * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0 * * 2) is done by a cunning combination of writes to an offset slightly - * less than the maximum memory reported by 0x10020C, then seeing if - * the test pattern can be read back. This then affects bits 12-15 of + * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing + * if the test pattern can be read back. This then affects bits 12-15 of * NV_PFB_CFG0 * * In this context a "cunning combination" may include multiple reads diff --git a/src/nv_setup.c b/src/nv_setup.c index 84b3c37..a66afb9 100644 --- a/src/nv_setup.c +++ b/src/nv_setup.c @@ -349,7 +349,7 @@ static void nv10GetConfig(ScrnInfoPtr pScrn) pNv->RamAmountKBytes = (((PCI_SLOT_READ_LONG(1, 0x84) >> 4) & 127) + 1) * 1024; nForce_check_dimms(pScrn); } else - pNv->RamAmountKBytes = (nvReadFB(pNv, NV_PFB_020C) & 0xFFF00000) >> 10; + pNv->RamAmountKBytes = (nvReadFB(pNv, NV_PFB_CSTATUS) & 0xFFF00000) >> 10; if (pNv->RamAmountKBytes > 256*1024) pNv->RamAmountKBytes = 256*1024; diff --git a/src/nvreg.h b/src/nvreg.h index f41bc55..647a141 100644 --- a/src/nvreg.h +++ b/src/nvreg.h @@ -141,7 +141,7 @@ #define NV_PFB_BOOT_0 0x00100000 #define NV_PFB_CFG0 0x00100200 #define NV_PFB_CFG1 0x00100204 -#define NV_PFB_020C 0x0010020C +#define NV_PFB_CSTATUS 0x0010020C #define NV_PFB_REFCTRL 0x00100210 # define NV_PFB_REFCTRL_VALID_1 (1 << 31) #define NV_PFB_PAD 0x0010021C |