pre-nv50: use nvidia's names for PCRTC regs where known

Mostly adding 'P' to the previous NV_CTRC regs -- either when known
correct, or when totally unknown (eg NV_PCRTC_850);  made-up names
untouched.  Lack of code changes checked with cpp.

Unused defines removed too.

7 files changed, 79 insertions, 81 deletions

diff --git a/src/nouveau_xv.c b/src/nouveau_xv.c
index a2a8fcd..246647b 100644
--- a/src/nouveau_xv.c
+++ b/src/nouveau_xv.c
@@ -841,22 +841,22 @@ NV_set_action_flags(ScrnInfoPtr pScrn, DrawablePtr pDraw, NVPortPrivPtr pPriv,
 			 * already here
 			 */
 			if (pPriv->overlayCRTC == 1) {
-				NVWriteCRTC(pNv, 0, NV_CRTC_FSEL,
-					    NVReadCRTC(pNv, 0, NV_CRTC_FSEL) |
+				NVWriteCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL,
+					    NVReadCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL) |
 					    NV_CRTC_FSEL_OVERLAY);
-				NVWriteCRTC(pNv, 1, NV_CRTC_FSEL,
-					    NVReadCRTC(pNv, 1, NV_CRTC_FSEL) &
+				NVWriteCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL,
+					    NVReadCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL) &
 					    ~NV_CRTC_FSEL_OVERLAY);
 				pPriv->overlayCRTC = 0;
 			}
 		} else
 		if ((crtc & (1 << 1))) {
 			if (pPriv->overlayCRTC == 0) {
-				NVWriteCRTC(pNv, 1, NV_CRTC_FSEL,
-					    NVReadCRTC(pNv, 1, NV_CRTC_FSEL) |
+				NVWriteCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL,
+					    NVReadCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL) |
 					    NV_CRTC_FSEL_OVERLAY);
-				NVWriteCRTC(pNv, 0, NV_CRTC_FSEL,
-					    NVReadCRTC(pNv, 0, NV_CRTC_FSEL) &
+				NVWriteCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL,
+					    NVReadCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL) &
 					    ~NV_CRTC_FSEL_OVERLAY);
 				pPriv->overlayCRTC = 1;
 			}
diff --git a/src/nv10_xv_ovl.c b/src/nv10_xv_ovl.c
index 2384c38..5dc696c 100644
--- a/src/nv10_xv_ovl.c
+++ b/src/nv10_xv_ovl.c
@@ -205,8 +205,10 @@ NV10SetOverlayPortAttribute(ScrnInfoPtr pScrn, Atom attribute,
                 if ((value < 0) || (value > 1))
                         return BadValue;
                 pPriv->overlayCRTC = value;
-                NVWriteCRTC(pNv, value, NV_CRTC_FSEL, NVReadCRTC(pNv, value, NV_CRTC_FSEL) | NV_CRTC_FSEL_OVERLAY);
-                NVWriteCRTC(pNv, !value, NV_CRTC_FSEL, NVReadCRTC(pNv, !value, NV_CRTC_FSEL) & ~NV_CRTC_FSEL_OVERLAY);
+                NVWriteCRTC(pNv, value, NV_PCRTC_ENGINE_CTRL,
+			    NVReadCRTC(pNv, value, NV_PCRTC_ENGINE_CTRL) | NV_CRTC_FSEL_OVERLAY);
+                NVWriteCRTC(pNv, !value, NV_PCRTC_ENGINE_CTRL,
+			    NVReadCRTC(pNv, !value, NV_PCRTC_ENGINE_CTRL) & ~NV_CRTC_FSEL_OVERLAY);
         } else
                 return BadMatch;
 
diff --git a/src/nv_crtc.c b/src/nv_crtc.c
index 2e87a15..85d0d8b 100644
--- a/src/nv_crtc.c
+++ b/src/nv_crtc.c
@@ -555,13 +555,13 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 	}
 
 	/* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
-	regp->cursorConfig = NV_CRTC_CURSOR_CONFIG_64LINES |
-			     NV_CRTC_CURSOR_CONFIG_64PIXELS |
+	regp->cursorConfig = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
+			     NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
 			     NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
 	if (pNv->alphaCursor)
-		regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_32BPP;
+		regp->cursorConfig |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
 	if (mode->Flags & V_DBLSCAN)
-		regp->cursorConfig |= NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN;
+		regp->cursorConfig |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
 
 	/* Unblock some timings */
 	regp->CRTC[NV_CIO_CRE_53] = 0;
@@ -600,10 +600,10 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
 
 	if (pNv->twoHeads)
 		/* This is what the blob does */
-		regp->unk850 = NVReadCRTC(pNv, 0, NV_CRTC_0850);
+		regp->unk850 = NVReadCRTC(pNv, 0, NV_PCRTC_850);
 
 	if (pNv->twoHeads)
-		regp->gpio_ext = NVReadCRTC(pNv, 0, NV_CRTC_GPIO_EXT);
+		regp->gpio_ext = NVReadCRTC(pNv, 0, NV_PCRTC_GPIO_EXT);
 
 	regp->config = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
 
@@ -913,7 +913,7 @@ static void nv_crtc_prepare(xf86CrtcPtr crtc)
 	NVBlankScreen(pNv, nv_crtc->head, true);
 
 	/* Some more preperation. */
-	NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
+	NVCrtcWriteCRTC(crtc, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
 	if (pNv->Architecture == NV_ARCH_40) {
 		uint32_t reg900 = NVCrtcReadRAMDAC(crtc, NV_RAMDAC_900);
 		NVCrtcWriteRAMDAC(crtc, NV_RAMDAC_900, reg900 & ~0x10000);
@@ -1257,7 +1257,7 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 		if (pNv->twoHeads)
 			/* setting FSEL *must* come before CIO_CRE_LCD, as writing CIO_CRE_LCD sets some
 			 * bits (16 & 17) in FSEL that should not be overwritten by writing FSEL */
-			NVCrtcWriteCRTC(crtc, NV_CRTC_FSEL, regp->head);
+			NVCrtcWriteCRTC(crtc, NV_PCRTC_ENGINE_CTRL, regp->head);
 
 		nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
 		nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
@@ -1270,12 +1270,12 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 		nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
 
 		crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_21);
-		NVCrtcWriteCRTC(crtc, NV_CRTC_CURSOR_CONFIG, regp->cursorConfig);
-		NVCrtcWriteCRTC(crtc, NV_CRTC_0830, regp->unk830);
-		NVCrtcWriteCRTC(crtc, NV_CRTC_0834, regp->unk834);
+		NVCrtcWriteCRTC(crtc, NV_PCRTC_CURSOR_CONFIG, regp->cursorConfig);
+		NVCrtcWriteCRTC(crtc, NV_PCRTC_830, regp->unk830);
+		NVCrtcWriteCRTC(crtc, NV_PCRTC_834, regp->unk834);
 		if (pNv->Architecture == NV_ARCH_40) {
-			NVCrtcWriteCRTC(crtc, NV_CRTC_0850, regp->unk850);
-			NVCrtcWriteCRTC(crtc, NV_CRTC_GPIO_EXT, regp->gpio_ext);
+			NVCrtcWriteCRTC(crtc, NV_PCRTC_850, regp->unk850);
+			NVCrtcWriteCRTC(crtc, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
 		}
 
 		if (pNv->Architecture == NV_ARCH_40) {
@@ -1287,7 +1287,7 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 		}
 	}
 
-	NVCrtcWriteCRTC(crtc, NV_CRTC_CONFIG, regp->config);
+	NVCrtcWriteCRTC(crtc, NV_PCRTC_CONFIG, regp->config);
 
 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
 	crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC1_INDEX);
@@ -1330,11 +1330,11 @@ static void nv_crtc_load_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 		crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_86);
 	}
 
-	NVCrtcWriteCRTC(crtc, NV_CRTC_START, regp->fb_start);
+	NVCrtcWriteCRTC(crtc, NV_PCRTC_START, regp->fb_start);
 
 	/* Setting 1 on this value gives you interrupts for every vblank period. */
-	NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_EN_0, 0);
-	NVCrtcWriteCRTC(crtc, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
+	NVCrtcWriteCRTC(crtc, NV_PCRTC_INTR_EN_0, 0);
+	NVCrtcWriteCRTC(crtc, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
 }
 
 static void nv_crtc_save_state_vga(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
@@ -1391,18 +1391,18 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 	crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_ILACE__INDEX);
 
 	if (pNv->Architecture >= NV_ARCH_10) {
-		regp->unk830 = NVCrtcReadCRTC(crtc, NV_CRTC_0830);
-		regp->unk834 = NVCrtcReadCRTC(crtc, NV_CRTC_0834);
+		regp->unk830 = NVCrtcReadCRTC(crtc, NV_PCRTC_830);
+		regp->unk834 = NVCrtcReadCRTC(crtc, NV_PCRTC_834);
 		if (pNv->Architecture == NV_ARCH_40) {
-			regp->unk850 = NVCrtcReadCRTC(crtc, NV_CRTC_0850);
-			regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_CRTC_GPIO_EXT);
+			regp->unk850 = NVCrtcReadCRTC(crtc, NV_PCRTC_850);
+			regp->gpio_ext = NVCrtcReadCRTC(crtc, NV_PCRTC_GPIO_EXT);
 		}
 		if (pNv->twoHeads)
-			regp->head = NVCrtcReadCRTC(crtc, NV_CRTC_FSEL);
-		regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_CRTC_CURSOR_CONFIG);
+			regp->head = NVCrtcReadCRTC(crtc, NV_PCRTC_ENGINE_CTRL);
+		regp->cursorConfig = NVCrtcReadCRTC(crtc, NV_PCRTC_CURSOR_CONFIG);
 	}
 
-	regp->config = NVCrtcReadCRTC(crtc, NV_CRTC_CONFIG);
+	regp->config = NVCrtcReadCRTC(crtc, NV_PCRTC_CONFIG);
 
 	crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH3__INDEX);
 	crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_SCRATCH4__INDEX);
@@ -1426,7 +1426,7 @@ static void nv_crtc_save_state_ext(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
 		crtc_rd_cio_state(crtc, regp, NV_CIO_CRE_86);
 	}
 
-	regp->fb_start = NVCrtcReadCRTC(crtc, NV_CRTC_START);
+	regp->fb_start = NVCrtcReadCRTC(crtc, NV_PCRTC_START);
 }
 
 static void nv_crtc_save_state_ramdac(xf86CrtcPtr crtc, RIVA_HW_STATE *state)
@@ -1563,10 +1563,9 @@ void NVCrtcSetBase(xf86CrtcPtr crtc, int x, int y)
 	else
 		start += pNv->FB->offset;
 
-	/* 30 bits addresses in 32 bits according to haiku */
 	start &= ~3;
 	pNv->ModeReg.crtc_reg[nv_crtc->head].fb_start = start;
-	NVCrtcWriteCRTC(crtc, NV_CRTC_START, start);
+	NVCrtcWriteCRTC(crtc, NV_PCRTC_START, start);
 
 	crtc->x = x;
 	crtc->y = y;
diff --git a/src/nv_dac.c b/src/nv_dac.c
index b229006..de8e4c4 100644
--- a/src/nv_dac.c
+++ b/src/nv_dac.c
@@ -208,16 +208,16 @@ NVDACInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
     nvReg->fifo = nvReadCurVGA(pNv, 0x1c) & ~(1<<5);
 
     if(pNv->crtc_active[1]) {
-       nvReg->head  = NVReadCRTC(pNv, 0, NV_CRTC_FSEL) & ~0x00001000;
-       nvReg->head2 = NVReadCRTC(pNv, 1, NV_CRTC_FSEL) | 0x00001000;
+       nvReg->head  = NVReadCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL) & ~0x00001000;
+       nvReg->head2 = NVReadCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL) | 0x00001000;
        nvReg->crtcOwner = 3;
        nvReg->pllsel |= 0x20000800;
        nvReg->vpll = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL);
        if(pNv->two_reg_pll) 
           nvReg->vpllB = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL_B);
     } else if(pNv->twoHeads) {
-       nvReg->head  =  NVReadCRTC(pNv, 0, NV_CRTC_FSEL) | 0x00001000;
-       nvReg->head2 =  NVReadCRTC(pNv, 1, NV_CRTC_FSEL) & ~0x00001000;
+       nvReg->head  =  NVReadCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL) | 0x00001000;
+       nvReg->head2 =  NVReadCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL) & ~0x00001000;
        nvReg->crtcOwner = 0;
        nvReg->vpll2 = NVReadRAMDAC(pNv, 0, NV_RAMDAC_VPLL2);
        if(pNv->two_reg_pll) 
diff --git a/src/nv_hw.c b/src/nv_hw.c
index dc46074..7a9db84 100644
--- a/src/nv_hw.c
+++ b/src/nv_hw.c
@@ -1039,8 +1039,8 @@ void NVLoadStateExt (
 
     if(pNv->Architecture >= NV_ARCH_10) {
         if(pNv->twoHeads) {
-           NVWriteCRTC(pNv, 0, NV_CRTC_FSEL, state->head);
-           NVWriteCRTC(pNv, 1, NV_CRTC_FSEL, state->head2);
+           NVWriteCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL, state->head);
+           NVWriteCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL, state->head2);
         }
         temp = nvReadCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC);
         nvWriteCurRAMDAC(pNv, NV_RAMDAC_NV10_CURSYNC, temp | (1 << 25));
@@ -1055,9 +1055,9 @@ void NVLoadStateExt (
         nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
         nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
 
-        nvWriteCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG, state->cursorConfig);
-        nvWriteCurCRTC(pNv, NV_CRTC_0830, state->displayV - 3);
-        nvWriteCurCRTC(pNv, NV_CRTC_0834, state->displayV - 1);
+        nvWriteCurCRTC(pNv, NV_PCRTC_CURSOR_CONFIG, state->cursorConfig);
+        nvWriteCurCRTC(pNv, NV_PCRTC_830, state->displayV - 3);
+        nvWriteCurCRTC(pNv, NV_PCRTC_834, state->displayV - 1);
     
         if(pNv->FlatPanel) {
            if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
@@ -1111,8 +1111,8 @@ void NVLoadStateExt (
     }
     nvWriteCurRAMDAC(pNv, NV_RAMDAC_GENERAL_CONTROL, state->general);
 
-    nvWriteCurCRTC(pNv, NV_CRTC_INTR_EN_0, 0);
-    nvWriteCurCRTC(pNv, NV_CRTC_INTR_0, NV_CRTC_INTR_VBLANK);
+    nvWriteCurCRTC(pNv, NV_PCRTC_INTR_EN_0, 0);
+    nvWriteCurCRTC(pNv, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
 }
 
 void NVUnloadStateExt
@@ -1150,13 +1150,13 @@ void NVUnloadStateExt
 
     if(pNv->Architecture >= NV_ARCH_10) {
         if(pNv->twoHeads) {
-           state->head     = NVReadCRTC(pNv, 0, NV_CRTC_FSEL);
-           state->head2    = NVReadCRTC(pNv, 1, NV_CRTC_FSEL);
+           state->head     = NVReadCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL);
+           state->head2    = NVReadCRTC(pNv, 1, NV_PCRTC_ENGINE_CTRL);
            state->crtcOwner = nvReadCurVGA(pNv, NV_CIO_CRE_44);
         }
         state->extra = nvReadCurVGA(pNv, NV_CIO_CRE_EBR_INDEX);
 
-        state->cursorConfig = nvReadCurCRTC(pNv, NV_CRTC_CURSOR_CONFIG);
+        state->cursorConfig = nvReadCurCRTC(pNv, NV_PCRTC_CURSOR_CONFIG);
 
         if((pNv->Chipset & 0x0ff0) == CHIPSET_NV11) {
            state->dither = nvReadCurRAMDAC(pNv, NV_RAMDAC_DITHER_NV11);
@@ -1181,7 +1181,7 @@ void NVSetStartAddress (
     CARD32 start
 )
 {
-    nvWriteCurCRTC(pNv, NV_CRTC_START, start);
+    nvWriteCurCRTC(pNv, NV_PCRTC_START, start);
 }
 
 uint32_t nv_pitch_align(NVPtr pNv, uint32_t width, int bpp)
diff --git a/src/nv_setup.c b/src/nv_setup.c
index 2a75f4f..23f1632 100644
--- a/src/nv_setup.c
+++ b/src/nv_setup.c
@@ -612,8 +612,8 @@ NVCommonSetup(ScrnInfoPtr pScrn)
 		tvA = !(nvReadCurVGA(pNv, NV_CIO_CRE_LCD__INDEX) & 0x01);
 	    }
 	    
-	    oldhead = NVReadCRTC(pNv, 0, NV_CRTC_FSEL);
-	    NVWriteCRTC(pNv, 0, NV_CRTC_FSEL, oldhead | 0x00000010);
+	    oldhead = NVReadCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL);
+	    NVWriteCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL, oldhead | 0x00000010);
 	    
 	    monitorA = NVProbeDDC(pScrn, 0);
 	    monitorB = NVProbeDDC(pScrn, 1);
@@ -726,7 +726,7 @@ NVCommonSetup(ScrnInfoPtr pScrn)
 	    if(implementation == CHIPSET_NV11)
 		cr44 = pNv->crtc_active[1] * 0x3;
 	    
-	    NVWriteCRTC(pNv, 0, NV_CRTC_FSEL,  oldhead);
+	    NVWriteCRTC(pNv, 0, NV_PCRTC_ENGINE_CTRL,  oldhead);
 
 	    nvWriteCurVGA(pNv, NV_CIO_CRE_44, cr44);
 	    NVSelectHeadRegisters(pScrn, pNv->crtc_active[1]);
diff --git a/src/nvreg.h b/src/nvreg.h
index 50914cc..02c62c0 100644
--- a/src/nvreg.h
+++ b/src/nvreg.h
@@ -160,35 +160,32 @@
 #	define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT	(8 << 12)
 #define NV_PEXTDEV_BOOT_3		0x0010100c
 
-#define NV_CRTC_INTR_0			0x00600100
-#	define NV_CRTC_INTR_VBLANK			(1<<0)
-#define NV_CRTC_INTR_EN_0		0x00600140
-#define NV_CRTC_START			0x00600800
-#define NV_CRTC_CONFIG			0x00600804
-	#define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA	1
-	#define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC	2
-#define NV_CRTC_CURSOR_ADDRESS		0x0060080C
-#define NV_CRTC_CURSOR_CONFIG		0x00600810
-#	define NV_CRTC_CURSOR_CONFIG_ENABLE		(1 << 0)
-#	define NV_CRTC_CURSOR_CONFIG_DOUBLE_SCAN	(1 << 4)
+#define NV_PCRTC_INTR_0					0x00600100
+#	define NV_PCRTC_INTR_0_VBLANK				(1 << 0)
+#define NV_PCRTC_INTR_EN_0				0x00600140
+#define NV_PCRTC_START					0x00600800
+#define NV_PCRTC_CONFIG					0x00600804
+#	define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA		(1 << 0)
+#	define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC		(2 << 0)
+#define NV_PCRTC_CURSOR_CONFIG				0x00600810
+#	define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE		(1 << 0)
+#	define NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE	(1 << 4)
 #	define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM	(1 << 8)
-#	define NV_CRTC_CURSOR_CONFIG_32BPP		(1 << 12)
-#	define NV_CRTC_CURSOR_CONFIG_64PIXELS		(1 << 16)
-#	define NV_CRTC_CURSOR_CONFIG_32LINES		(2 << 24)
-#	define NV_CRTC_CURSOR_CONFIG_64LINES		(4 << 24)
-#	define NV_CRTC_CURSOR_CONFIG_ALPHA_BLEND	(1 << 28)
+#	define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32		(1 << 12)
+#	define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64		(1 << 16)
+#	define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_32		(2 << 24)
+#	define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64		(4 << 24)
+#	define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ALPHA		(1 << 28)
 
 /* note: PCRTC_GPIO is not available on nv10, and in fact aliases 0x600810 */
-#define NV_CRTC_GPIO			0x00600818
-#define NV_CRTC_GPIO_EXT		0x0060081c
-#define NV_CRTC_0830			0x00600830
-#define NV_CRTC_0834			0x00600834
-#define NV_CRTC_0850			0x00600850
-#define NV_CRTC_FSEL			0x00600860
-#	define NV_CRTC_FSEL_I2C				(1<<4)
-#	define NV_CRTC_FSEL_TVOUT1			(1<<8)
-#	define NV_CRTC_FSEL_TVOUT2			(2<<8)
-#	define NV_CRTC_FSEL_OVERLAY			(1<<12)
+#define NV_PCRTC_GPIO					0x00600818
+#define NV_PCRTC_GPIO_EXT				0x0060081c
+#define NV_PCRTC_830					0x00600830
+#define NV_PCRTC_834					0x00600834
+#define NV_PCRTC_850					0x00600850
+#define NV_PCRTC_ENGINE_CTRL				0x00600860
+#	define NV_CRTC_FSEL_I2C					(1 << 4)
+#	define NV_CRTC_FSEL_OVERLAY				(1 << 12)
 
 #define NV_PRMCIO_ARX			0x006013c0
 #define NV_PRMCIO_AR__WRITE		0x006013c0