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authorFrancisco Jerez <currojerez@riseup.net>2010-06-17 12:42:14 +0200
committerFrancisco Jerez <currojerez@riseup.net>2010-06-17 16:15:40 +0200
commitfe31a1e090514ab05c069ff187bbf3f12576318f (patch)
tree7b2e9560f700c8b87b0ce6f633f110f7398a3e79
parent48f4092e87397ca2b01d5cdb016a302fa31fcca5 (diff)
drm/nouveau: Don't clear AGPCMD completely on INIT_RESET.
We just need to clear the SBA and ENABLE bits to reset the AGP controller: If the AGP bridge was configured to use "fast writes", clearing the FW bit would break the subsequent MMIO writes and eventually end with a lockup. Note that all the BIOSes I've seen do the same as we did (it works for them because they don't use MMIO), OTOH the blob leaves FW untouched. Signed-off-by: Francisco Jerez <currojerez@riseup.net>
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index ee36f8ff3ad2..903e72b305bf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2126,7 +2126,8 @@ init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
/* no iexec->execute check by design */
pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
- bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
+ bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
+
bios_wr32(bios, reg, value1);
udelay(10);