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2014-09-01i965/fs: Don't segfault when debug-logging a null programJason Ekstrand1-2/+2
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-01i965/vec4: Don't segfault when debug-logging a null programJason Ekstrand1-2/+2
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-01glsl_to_tgsi: allocate and enlarge arrays for temporaries on demandMarek Olšák1-18/+33
This fixes crashes if the number of temporaries is greater than 4096. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66184 v2: added fail paths for realloc failures Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-09-01i965/fs: don't use ir->shadow_comparitor in emit_texture_*Connor Abbott2-7/+5
Signed-off-by: Connor Abbott <connor.abbott@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-01i965/fs: don't pass ir_variable * to emit_samplepos_setup()Connor Abbott3-5/+4
We were only using it to get at its type, which we already know because it's a builtin variable. Signed-off-by: Connor Abbott <connor.abbott@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-09-01i965/fs: don't pass ir_variable * to emit_frontfacing_interpolation()Connor Abbott4-6/+6
We were only using it to get at its type, which we already know because it's a builtin variable. v2 (Ken): Rebase on Matt's optimized gl_FrontFacing calculations. Signed-off-by: Connor Abbott <connor.abbott@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-31i965: Fix GPU hangs when INTEL_DEBUG=no16 is set.Kenneth Graunke1-1/+2
The replicated data clear shader needs to be SIMD16, or else the GPU will hang. So, compile it even if INTEL_DEBUG=no16 is set. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-01mesa: fix make tarballsEmil Velikov1-1/+2
Current method of generating distribution tar-balls involves manually invoking make + target name in the appropriate places. This temporary solution is used until we get 'make dist' working. Currently it does not work, as in order to have the target (which is also a filename) available in the final Makefile we need to add a PHONY target + use the correct target name. Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-31i965/vec4: Remove try_emit_saturateAbdiel Janulgue2-22/+0
Now that saturate is implemented natively as an instruction, we can cut down on unneeded functionality. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965/fs: Refactor try_emit_saturateAbdiel Janulgue1-15/+8
v3: Since the fs backend can emit saturate as a separate instruction, there is no need to detect for min/max instructions and to rewrite the instruction tree accordingly. On the other hand, we don't need to emit a separate saturated mov either when the expression generating src can do saturate directly. v4: Add can_do_saturate() check before enabling saturate modifer (Ken) Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31ir_to_mesa, glsl_to_tgsi: Remove try_emit_saturateAbdiel Janulgue2-99/+0
Now that saturate is implemented natively as instruction, we can cut down on unneeded functionality. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965/vec4: Allow propagation of instructions with saturate flag to selAbdiel Janulgue1-27/+58
When sel conditon is bounded within 0 and 1.0. This allows code as: mov.sat a b sel.ge dst a 0.25F To be propagated as: sel.ge.sat dst b 0.25F v3: - Syntax clarifications in inst->saturate assignment - Remove extra parenthesis when assigning src_reg value from copy_entry (Matt Turner) v4: - Take channels into consideration when propagating saturated instructions. Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965/fs: Allow propagation of instructions with saturate flag to selAbdiel Janulgue1-1/+17
When sel conditon is bounded within 0 and 1.0. This allows code as: mov.sat a b sel.ge dst a 0.25F To be propagated as: sel.ge.sat dst b 0.25F v3: Syntax clarifications in inst->saturate assignment (Matt Turner) Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31yi965/vec4: Add support for ir_unop_saturateAbdiel Janulgue1-0/+4
Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965/fs: Add support for ir_unop_saturateAbdiel Janulgue2-0/+5
Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31ir_to_mesa, glsl_to_tgsi: Add support for ir_unop_saturateAbdiel Janulgue2-0/+12
Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31ir_to_mesa, glsl_to_tgsi: lower ir_unop_saturateAbdiel Janulgue2-2/+9
Needed when vertex programs doesn't allow saturate Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965/vec4/fs: Count loops in shader debugAbdiel Janulgue2-4/+8
Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965/vec4: inline generate_vec4_instruction() within generate_code()Abdiel Janulgue2-316/+296
Suggested by Matt. This patch combines and moves back the code-generation functions from generate_vec4_instruction() into generate_code(). Makes generate_code() a bit larger, but helps us to count loops in a straightforward manner. Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-31i965: Add 2x MSAA support to Broadwell fast clear code.Kenneth Graunke1-0/+1
According to the cited documentation section (but in the newer docs), x_scaledown is the same for 2x and 4x MSAA. +47 piglits. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83081 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: "10.3" <mesa-stable@lists.freedesktop.org>
2014-08-30i965/vec4: Update register coalescing test.Matt Turner1-4/+1
In commit 04895f5c I added support for reswizzling writemasks. This test was checking that we didn't support this. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82881
2014-08-30i965: Use unreachable() to silence warning.Matt Turner1-2/+1
brw_meta_fast_clear.c:211:17: warning: 'x_scaledown' may be used uninitialized in this function [-Wmaybe-uninitialized] unsigned int x_scaledown, y_scaledown; Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29glsl: Eliminate ir_variable::data.atomic.buffer_indexIan Romanick2-2/+2
Just use ir_variable::data.binding... because that's the where the binding is stored for everything else that can use layout(binding=). Valgrind massif results for a trimmed apitrace of dota2: n time(i) total(B) useful-heap(B) extra-heap(B) stacks(B) Before (32-bit): 50 40,564,927,443 69,185,408 63,683,871 5,501,537 0 After (32-bit): 74 40,580,119,657 69,186,544 63,506,327 5,680,217 0 Before (64-bit): 59 36,822,048,449 96,526,888 89,113,000 7,413,888 0 After (64-bit): 89 36,822,971,897 96,526,616 88,735,296 7,791,320 0 A real savings of 173KiB on 32-bit and 368KiB on 64-bit. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29mesa: Delete ctx->GeometryProgram.Cache.Kenneth Graunke2-5/+0
The VertexProgram and FragmentProgram have a Cache member for dealing with fixed function programs. There are no fixed function geometry programs, so this should never have existed, and was just copy and pasted. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-08-30mesa: fix fallback texture for cube map arrayRoland Scheidegger1-6/+10
mesa was creating a cube map array texture with just one layer, which is not legal. This caused an assertion failure when using that texture later in llvmpipe (when enabling cube map arrays) since it verifies the number of layers in the view is divisible by 6 (the sampling code might well crash randomly otherwise) with piglit glsl-resource-not-bound CubeArray -fbo -auto. v2: use appropriately sized texel array... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
2014-08-28i965: Mark BRW_CONDITIONAL_R as Gen <= 5.Matt Turner1-1/+1
2014-08-28i965/disasm: Show jump count for if/iff/halt.Matt Turner1-1/+1
These instructions don't have pop count. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-28i965/disasm: Disassemble JMPI's source properly.Matt Turner1-1/+2
The source can be a register as well as an immediate, and disassembling a register as an immediate can have some strange results. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-28i965/disasm: Add break/cont/halt to list of has_uip().Matt Turner1-1/+4
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-28i965/disasm: Disassemble Z/NZ conditional modifiers as .z/.nz.Matt Turner1-2/+2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-27gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri1-0/+3
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-27mesa: implement GL_MAX_VERTEX_ATTRIB_STRIDETimothy Arceri4-0/+31
V2: moved test for the VertexAttrib*Pointer() functions to update_array(), and made constant available for drivers to set Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-22i965: Disable try_emit_b2f_of_compare on Gen4-6.Kenneth Graunke1-0/+7
The optimization relies on CMP setting the destination to 0, which is equivalent to 0.0f. However, early platforms only set the least significant byte, leaving the other bits undefined. So, we must disable the optimization on those platforms. Oddly, Sandybridge wasn't reported as broken. The PRM states that it only sets the LSB, but the internal documentation says that it follows the IVB behavior. Since it wasn't reported as broken, we believe it really does follow the IVB behavior. v2: Allow the optimization on Sandybridge (requested by Matt). +32 piglits on Ironlake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-22i965/fs: Preserve CFG in predicated break pass.Matt Turner1-4/+25
Operating on this code, B0: ... cmp.ne.f0(8) (+f0) if(8) B1: break(8) B2: endif(8) We can delete B2 without attempting to merge any blocks, since the break/continue instruction necessarily ends the previous block. After deleting the if instruction, we attempt to merge blocks B0 and B1. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/fs: Rename variable in predicated break pass.Matt Turner1-7/+8
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/fs: Preserve CFG in the SEL peephole.Matt Turner1-6/+9
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965: Preserve CFG when deleting dead control flow.Matt Turner1-9/+45
This pass deletes an IF/ELSE/ENDIF or IF/ENDIF sequence, or the ELSE in an ELSE/ENDIF sequence. In the typical case (where IF and ENDIF) aren't the only instructions in their basic blocks, we can simply remove the instructions (implicitly deleting the block containing only the ELSE), and attempt to merge blocks B0 and B2 together. B0: ... (+f0) if(8) B1: else(8) B2: endif(8) ... If the IF or ENDIF instructions are the only instructions in their respective basic blocks (which are deleted by the removal of the instructions), we'll want to instead merge the next blocks. Both B0 and B2 are possibly removed by the removal of if & endif. Same situation for if/endif. E.g., in the following example we'd remove blocks B1 and B2, and then attempt to combine B0 and B3. B0: ... B1: (+f0) if(8) B2: endif(8) B3: ... Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/cfg: Add functions to combine basic blocks.Matt Turner2-0/+54
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/cfg: Point to bblock_t containing associated control flowMatt Turner3-27/+15
... rather than pointing directly to the associated instruction. This will let us set the block containing the IF statement's else-pointer to NULL, when we delete a useless ELSE instruction, as in the case (+f0) if(8) ... else(8) endif(8) Also, remove the pointer to the ENDIF, since it's unused, and it was also potentially wrong, in the case of a basic block containing both an ENDIF and an IF instruction: endif(8) cmp.ne.f0(8) ... (+f0) if(8) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/fs: Preserve CFG in register allocation.Matt Turner2-10/+14
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965: Use basic-block aware insertion/removal functions.Matt Turner9-40/+50
To avoid invalidating and recreating the control flow graph. Also stop invalidating the CFG in places we didn't add or remove an instruction. cfg calculations: 202951 -> 80307 (-60.43%) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965: Add invalidate_cfg parameter to invalidate_live_intervals().Matt Turner5-7/+9
Will let us avoid invalidating the CFG if the optimization pass has removed instructions using the new basic block methods. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965: Add basic-block aware backend_instruction::insert_* methods.Matt Turner2-0/+52
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965: Add a basic-block aware backend_instruction::remove method.Matt Turner2-0/+50
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/cfg: Add a function to remove a block from the cfg.Matt Turner2-4/+59
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965/cfg: Add functions to test if a block is a successor/predecessor.Matt Turner2-0/+26
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22i965: Fix JIP/UIP calculations.Matt Turner1-8/+6
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82846 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82929
2014-08-21dri/radeon: nuke the remaining references to sareaEmil Velikov3-11/+0
Remainder of the dri1 times. Cc: Marek Olšák <marek.olsak@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-21dri/radeon: cleanup the radeon_context vtblEmil Velikov8-163/+0
Remove the set-but-unused, and set-but-empty vtable entries. Most likely a leftover from the dri1 days. Cc: Marek Olšák <marek.olsak@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-21dri/radeon: drop obsolete radeon_{dri,macros}.h headersEmil Velikov7-248/+2
Both have been unused for at least a couple of years. For example the last user of radeon_macros.h was removed with commit 8c11f0a88300f7bc3f05a12789c781ba0f4b3cc6 Author: Eric Anholt <eric@anholt.net> Date: Fri Oct 14 13:27:02 2011 -0700 radeon: Drop the legacy BO manager code. Cc: Marek Olšák <marek.olsak@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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