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2018-02-28winsys/amdgpu: request high addressesChristian König1-4/+12
We now have hopefully fixed all bugs regarding high addresses on Vega10 and Raven. Start to use the high range to make room for SVM in the low range. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-31winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2Christian König3-5/+27
When the kernel supports it set the local flag and stop adding those BOs to the BO list. Can probably be optimized much more. v2: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-24winsys/amdgpu: align VA allocations to fragment size v2Christian König3-0/+4
BOs larger than the minimum fragment size should have their VA alignet to at least the fragment size for optimal performance. v2: drop unused leftover from initial implementation Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-13svga: handle P016 format as wellChristian König1-0/+1
Fixes: 62cff793785 ("gallium: add P016 format") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100180 Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-03-13st/va: add config support for 10bit decoding v2Christian König2-4/+21
Advertise 10bpp support if the driver supports decoding to a P016 surface. v2: Advertise 10bpp for the decoder as well. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Mark Thompson <sw@jkqxz.net>
2017-03-13st/va: add support for allocating 10bpp surfacesChristian König1-9/+15
We support P010 and P016 as targets for 10bpp video decoding. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13st/va: add support for P010 and P016 formats v3Christian König4-3/+22
No hardware I know off can actually support P010 natively. But we can easily support P016 and as long as nobody decodes anything into the lower 6bits it doesn't make any difference to P010. v2: allow P0160 for post processing as well v3: fix post processing once more Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13st/va: clear the video surface on allocationChristian König1-4/+35
This makes debugging of decoding problems quite a bit easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13st/va: cleanup error handling in vlVaCreateSurfaces2Christian König1-25/+27
No need to have that twice. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13radeon/uvd: enable 10bit HEVC decode v2Christian König2-8/+20
Just use whatever the state tracker allocated. v2: fix msb mode Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13radeon/UVD: fix the decoding target pitch calculationChristian König1-1/+1
The firmware expects the value in pixel not bytes. Didn't made a difference so far because we only used 8bpp surfaces. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13vl/video_buffer: add support for P016Christian König1-0/+10
Just simply the description of the planes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13gallium: add P016 formatChristian König4-0/+42
Same layout as NV12, but 16bit per channel instead of 8. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-01-23st/va: make sure that we call begin_frame() only once v2Christian König2-3/+9
This fixes "st/va: delay calling begin_frame until we have all parameters". v2: call begin frame after decoder (re)creation as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Tested-by: Andy Furniss <adf.lists@gmail.com>
2017-01-03vl/zscan: fix "Fix trivial sign compare warnings"Christian König1-1/+1
The variable actually needs to be signed, otherwise converting it to a float doesn't work as expected. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98914 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Cc: "13.0" <mesa-stable@lists.freedesktop.org> Fixes: 1fb4179f927 ("vl: Fix trivial sign compare warnings")
2016-08-29st/vdpau: Revert "change the order in which filters are applied(v3)"Christian König1-18/+10
This reverts commit 09dff7ae2e179d5a3490481762c6bd3d50430c9f. Turned out this can cause some artifacts in the output. Let's revert it for now until we have sorted out all issues. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
2016-07-18radeon/uvd: add session context buffer for polaris 10/11 v2Christian König2-0/+21
This way we have unlimited UVD sessions. v2: only enable it when kernel supports it as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-14st/mesa: fix reference counting bug in st_vdpauChristian König1-2/+8
Otherwise we leak the resources created for the DMA-buf descriptors. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: 12.0 <mesa-stable@lists.freedesktop.org> Tested-and-Reviewed by: Leo Liu <leo.liu@amd.com> Ack-by: Tom St Denis <tom.stdenis@amd.com>
2016-07-08radeon/uvd: simplify sending context buffer messageChristian König1-4/+1
Just send it whenever it is allocated. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08radeon/uvd: fix contex buffer destruction in the error pathChristian König1-6/+2
Destroying a not allocated buffer is harmless. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08radeon/uvd: move polaris fw check into radeon_video.c v2Christian König2-11/+13
It's actually not very clever to claim to support H.264 and then fail to create a decoder. v2: prefix FW macro with UVD_. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08radeon/video: fix coding style in radeon_video.c v2Christian König1-15/+15
v2: fix other tabs as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-06-16st/vdpau: we support lumakeying nowChristian König1-0/+1
Signed-off-by: Christian König <christian.koenig@amd.com>
2016-06-16vl: support luma keying for interlaced surfaces as wellChristian König1-35/+41
We had the CSC code twice in there, factor it out into a separate function. Signed-off-by: Christian König <christian.koenig@amd.com>
2016-06-02radeon/uvd: fix the H264 level for Tonga v2Christian König1-1/+1
We support 5.2 for a while now. v2: we even support 5.2 for H264, 5.1 is for HEVC. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: <mesa-stable@lists.freedesktop.org>
2016-03-30r600: ignore PIPE_BIND_LINEAR in *_is_format_supportedChristian König2-0/+10
Similar to radeonsi linear layout should work for all not compressed or depth/stencil formats. Fixes issues with VDPAU on r600. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2016-03-29st/mesa: implement new DMA-buf based VDPAU interop v2Christian König1-49/+132
Avoid using internal structures from another API. v2: rebase and moved includes so they don't cause problem when VDPAU isn't installed. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1) Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-03-29st/vdpau: implement the new DMA-buf based interop v2Christian König4-3/+116
That should allow us to get away from passing internal structures around. v2: rebased Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-03-29st/vdpau: move FormatRGBAToPipe into the interopChristian König5-28/+73
We are going to need that in the Mesa state tracker as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-03-29st/vdpau: add new interop interfaceChristian König2-1/+100
Use DMA-buf for the VDPAU interop interface instead of using internal structures. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-03-29st/vdpau: use linear layout for output surfacesChristian König1-1/+2
Works around a bug in radeonsi and tiling is actually not very beneficial in this use case. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-03-29radeonsi: ignore PIPE_BIND_LINEAR in si_is_format_supported v2Christian König1-0/+5
Linear layout should work for all not compressed or depth/stencil formats. v2: restrict it a bit more Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-17radeon/winsys: add layer support for BO exportChristian König4-0/+7
Add layer support to export individual array layers. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-17radeon/winsys: add offset support for BO import/exportChristian König5-18/+33
Add offset support to handle NV12 offsets as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-17gallium/winsys/drm: add layer to struct winsys_handleChristian König1-0/+5
For exporting a specific layer of an array texture. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-17gallium/winsys/drm: add offset to struct winsys_handleChristian König6-0/+13
We are going to need this for EGL_EXT_image_dma_buf_import. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-08st/mesa: conditionally enable GL_NV_vdpau_interopChristian König3-0/+9
Only enable it when we compile the state tracker as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-08radeon/uvd: disable MPEG1Christian König1-0/+1
The hardware simply doesn't support that correctly. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-01-19st/va: fix motion adaptive deinterlacingChristian König1-1/+1
Signed-off-by: Christian König <christian.koenig@amd.com>
2016-01-18st/va: add motion adaptive deinterlacing v2Christian König4-7/+82
v2: minor cleanup Signed-off-by: Christian König <christian.koenig@amd.com>
2016-01-12vl: use preferred format for deinterlacingChristian König1-1/+7
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12vl: improve motion adaptive deinterlacerChristian König2-22/+49
Handle other formats than YV12 as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12st/va: add BOB deinterlacing v2Christian König2-11/+79
Tested with MPV. v2: correctly handle compositor deinterlacing as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12st/va: add NV12 -> NV12 post processing v2Christian König2-37/+124
Usefull for mpv and GStreamer. v2: use common functionality for size adjustment. Signed-off-by: Indrajit-kumar Das <Indrajit-kumar.Das@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12st/va: use vl_video_buffer_adjust_sizeChristian König1-9/+4
Use the new helper function instead of open coding it. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12st/vdpau: use vl_video_buffer_adjust_sizeChristian König1-10/+3
Use the new helper function instead of open coding it. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12vl/buffers: extract vl_video_buffer_adjust_size helperChristian König2-8/+20
Useful for the state trackers as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-12st/va: make the implementation thread safe v2Christian König7-54/+199
Otherwise we might crash with MPV. v2: minor cleanups suggested on the list. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Julien Isorce <j.isorce@samsung.com> Tested-by: Julien Isorce <j.isorce@samsung.com>
2015-12-16st/va: remove fence handling v3Christian König5-22/+7
It's nonsense to drain the pipeline like this. v2: keep the drain for DMA-buf exports. v3: flush before the export and after compositing and add TODO comment. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Julien Isorce <j.isorce@samsung.com> Tested-by: Julien Isorce <j.isorce@samsung.com>
2015-12-15st/va: remove nonesense HEVC picture id handlingChristian König1-5/+0
The picture id in this case is a VA-API surface handle, checking for a certain value can't be correct. Signed-off-by: Christian König <christian.koenig@amd.com>
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