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2023-12-06radv,aco: declare PS epilog VGPR arguments for depth/stencil/samplemaskSamuel Pitoiset3-0/+14
Depth/stencil/samplemask inputs are first to match create_fs_jump_to_epilog(). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06radv: prepare the PS epilog key for exporting MRTZ on RDNA3Samuel Pitoiset6-1/+24
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06radv: determine if MRTZ needs to be exported via PS epilogsSamuel Pitoiset4-2/+19
For GFX11 only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06ac/nir: add an option to skip MRTZ exports in ac_nir_lower_ps()Samuel Pitoiset2-5/+15
On RDNA3, alpha to coverage needs to be exported through MRTZ when depth, stencil or samplemask are also exported. This option will allow us to export MRTZ from PS epilogs instead of the main FS. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06aco: export depth/stencil/samplemask in create_fs_jump_to_epilog()Samuel Pitoiset1-1/+13
This currently has no effects because the store_output instructions are removed earlier (in ac_nir_lower_ps). Though, this will be needed for exporting MRTZ from PS epilogs for alpha to coverage on RDNA3. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06radv: remove unused code for compiling PS epilogs as part of pipelinesSamuel Pitoiset6-140/+22
Since we switched to the "on-demand" path for GPL, this is dead code. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06radv: switch to on-demand PS epilogs for GPLSamuel Pitoiset2-9/+22
RADV currently has two paths for PS epilogs: - the first one is mostly used by GPL to compile fragment shader epilogs as part of the graphics pipeline. It's supposed to be optimal because fragment shader epilogs are compiled in the pipeline and eventually cached. - the second one (the "on-demand" path) is required when some dynamic states are used because otherwise it's just impossible to compile the fragment shader. These epilogs are compiled during cmdbuf recording when all needed info are known, they are also cached in memory. This is the main path for Zink. Having two different paths isn't ideal for maintenance but there is another problem. On RDNA3, alpha to coverage needs to be exported as part of MRTZ when either depth/stencil/samplemask are exported. The problem being that with GPL, the PSO multisample state can be NULL when the frag shader lib is created, which means that we can't know if atc needs to be exported or not, even if it's static. The solution seems to to always use on-demand fragment shader epilogs for GPL on RDNA3. So far, I think that switching to on-demand PS epilogs unconditionally for GPL shouldn't hurt performance and that will simplify a lot of things. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-05aco: insert p_end_wqm before p_jump_to_epilogRhys Perry1-0/+1
Otherwise, we can transition to exact before p_jump_to_epilog, then transition to WQM again and then back to exact: p_jump_to_epilog //transitions to exact p_logical_end //transitions to wqm p_end_wqm //transitions to exact We rely on ssa elimination to clean most of this up. fossil-db (navi21): Totals from 1 (0.00% of 79330) affected shaders: Instrs: 111 -> 110 (-0.90%) CodeSize: 572 -> 568 (-0.70%) Copies: 16 -> 15 (-6.25%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25440>
2023-11-21radv: rename ps_epilog_inputs to colors for PS epilogsSamuel Pitoiset3-3/+3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26231>
2023-11-21aco: rename color_exports to exports in create_fs_jump_to_epilog()Samuel Pitoiset1-6/+6
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26231>
2023-11-14radv: Use shader part caching helpers for VS prolog and PS/TCS epilog.Tatsuyuki Ishi4-207/+139
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028>
2023-11-14radv: Implement helpers for shader part caching.Tatsuyuki Ishi2-0/+98
Currently, shader part caching logic is duplicated between VS prolog and PS/TCS epilogs. This commit introduces a common abstraction to deduplicate the code. Additionally, there are a few design decisions that diverts from the current implementation: 1. A simple mutex is used instead of reader-writer lock. Prolog/epilog constructions are serialized, removing the need to free duplicate objects in case of a race. 2. A CS-local cache is used to quickly lookup an entry without holding a lock. This eliminates locking in over 99% of cases. 3. A set is used to reduce number of allocations. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028>
2023-11-13radv, aco: Rework VS prolog key handling.Tatsuyuki Ishi6-120/+45
The main change is to use struct radv_vs_prolog_key directly instead of the compressed representation to simplify an upcoming rework in prolog / epilog caching. In doing so the state struct pointer was replaced with an inline struct. Care was also taken to pre-mask all the states with the active attribute mask and other masks when it makes sense; this ensures that we don't accidentally use information not hashed into the key during compilation. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
2023-11-13radv: Remove last VS prolog reuse logic.Tatsuyuki Ishi2-6/+0
This was broken as the field was never assigned to. This will also be dropped from the upcoming prolog/epilog lookup rework, as it adds to code complexity while the benefit of saving one hash table memory access seems questionable. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
2023-10-10radeonsi: add ps epilog shader part buildQiang Yu1-1/+36
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
2023-10-10radeonsi: extract si_get_ps_epilog_args to be shared with acoQiang Yu3-35/+47
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
2023-10-10aco: do not fix_exports when program has epilogQiang Yu2-11/+3
PS with epilog does not need to fix_exports. And radeonsi use p_end_with_regs so does not have jump instruction at last. radeonsi may also have exec restore instruction, so may break before reach to p_end_with_regs. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco: compact ps expilog color export for radeonsiQiang Yu1-13/+12
radeonsi need to compact color export for ps epilog while radv does not. radv will fill empty color slot, so won't affected by this change. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco,radv: add radeonsi spec ps epilog codeQiang Yu4-12/+172
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco: simplify export_fs_mrt_colorQiang Yu1-85/+48
It's now used by ps epilog only. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco,radv: rename ps epilog info inputs to colorsQiang Yu3-7/+7
Will add other mrtz args for radeonsi. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco,radv: remove unused ps epilog info fieldsQiang Yu2-2/+0
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco: add create_fs_end_for_epilog for radeonsiQiang Yu2-2/+65
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10aco: remove p_end_with_regs from needs_exact()Qiang Yu1-2/+1
ps needs to handle wqm: 1. main part may compute with args from prolog in wqm mode, so prolog need to compute these args in wqm mode too. 2. prolog and main part need to end with exact exec, so next shader part which inherit previous shader part's exec won't do valid job for helper threads 1 need p_end_with_regs to operate in wqm mode and itself can't be exact, otherwise some move instruction added by it won't be in wqm mode so helper threads' compute result is not passed to next shader part as args. 2 is done by p_end_wqm added by finish_program automatically after p_end_with_regs. Piglit tests can trigger the problem: 1. gl-2.1-polygon-stipple-fs a. ps prolog call discard_if b. ps main pass wqm exec to epilog c. ps epilog export color for discarded pixel 2. fs-fwidth-color.shader_test a. ps prolog need to pass args computed in wqm mode b. set p_end_with_regs to exact will end wqm mode before the move instructions, so helper threads's result is not passed to next shader part Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-04nvk: Take GETPARAM_EXEC_PUSH_MAX into accountFaith Ekstrand3-3/+12
Reviewed-by: Danilo Krummrich <dakr@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25444>
2023-10-04drm-uapi: Sync nouveau_drm.hFaith Ekstrand1-0/+10
From https://cgit.freedesktop.org/drm-misc/ commit d59e75eef52d89201aaf5342a3ac23ddf3e9b112 Author: Danilo Krummrich <dakr@redhat.com> Date: Mon Oct 2 15:46:48 2023 +0200 drm/nouveau: exec: report max pushs through getparam Reviewed-by: Danilo Krummrich <dakr@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25444>
2023-09-14radv: Don't advertise features requiring PS epilogs with LLVMKonstantin Seurer1-4/+4
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25010>
2023-08-29aco: fix emitting TCS epilogs end on GFX9+Samuel Pitoiset1-6/+8
With merged shaders, the long-jump should be emitted inside the divergent if (ie. only for TCS invocations) and other non TCS invocations should just end the program. This fixes a bunch of failures with CTS by forcing TCS epilogs on RDNA2. Not sure how RadeonSI will handle that but maybe doing the merged wave info thing in epilogs would help. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24832>
2023-08-29radv: fix emitting TCS epilogs if TES and GS are linked on GFX9+Samuel Pitoiset1-1/+1
TES would be NULL because everything is merged to GS. Found by inspection. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>
2023-08-29radv: rename tcs_shader to tcs in radv_emit_tcs_epilog_state()Samuel Pitoiset1-8/+8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>
2023-08-24nvk: Plumb no_prefetch through to the DRM back-endFaith Ekstrand3-15/+30
Instead of using bit 23 of nvk_cmd_push::range for this, pass it as a separate bool. This lets us use the actual kernel flag with the new UAPI. Reviewed-by: Danilo Krummrich <dakr@redhat.com> Tested-by: Danilo Krummrich <dakr@redhat.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
2023-08-24drm-uapi: Sync nouveau_drm.hFaith Ekstrand1-1/+7
From https://cgit.freedesktop.org/drm-misc/ commit 443f9e0b1ab5e3b95abf8606097d13e30e2f2413 Author: Danilo Krummrich <dakr@redhat.com> Date: Wed Aug 23 20:15:34 2023 +0200 drm/nouveau: uapi: don't pass NO_PREFETCH flag implicitl Reviewed-by: Danilo Krummrich <dakr@redhat.com> Tested-by: Danilo Krummrich <dakr@redhat.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24840>
2023-08-24radv: stop declaring unused SGPR arguments for PS epilogsSamuel Pitoiset1-6/+0
ACO no longer requires these arguments. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24838>
2023-08-24radv: fix the per-patch data offset when TES isn't linked with TCSSamuel Pitoiset4-7/+16
When TCS and TES aren't linked together and TCS exports unused outputs, the per-patch data offset needs to be adjusted. This is similar to the LS-HS vertex stride when VS and TCS aren't linked together. This fixes a bunch of failures by forcing the driver to use TCS epilogs. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24776>
2023-08-22aco: implement create_tcs_jump_to_epilog()Samuel Pitoiset3-4/+128
This implements jumping from the main TCS to the epilog. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22aco: allow SGPRs operands with p_jump_to_epilogSamuel Pitoiset1-3/+5
For TCS epilogs, we will have to pass SGPRs. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22aco: adjust TCS epilogs for RADVSamuel Pitoiset2-6/+24
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22aco: fix jumping from main TCS to epilog on GFX9+Samuel Pitoiset1-2/+2
On GFX9+, VS is merged with TCS which means this function is called twice and the epilog was emitted in both shader parts. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22radv: add tcs_out_patch_fits_subgroup to radv_tcs_epilog_keySamuel Pitoiset2-0/+3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22radv: declare shader arguments for TCS epilogsSamuel Pitoiset2-1/+14
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22radv: stop declaring the scratch offset argument for TCS epilogsSamuel Pitoiset1-5/+0
ACO skip it for epilogs now. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22radv: use the maximum possible workgroup size for TCS epilogsSamuel Pitoiset1-1/+1
It's similar to when the patch control points value is dynamic. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-18radv: fix emitting TCS epilogs for GFX6-9Samuel Pitoiset1-3/+6
The number of SGPRs need to be adjusted. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24747>
2023-08-16radeonsi: add si_aco_build_shader_partQiang Yu2-0/+90
Now it only has tcs epilog build, will add more prolog/epilog to it. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
2023-08-16radeonsi: change si_fill_aco_options argsQiang Yu1-13/+12
Prepare to be shared with prolog/epilog generation which does not have si_shader param. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
2023-08-16radeonsi: add si_get_tcs_epilog_argsQiang Yu3-45/+64
For shared with aco tcs epilog creation. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
2023-08-16radeonsi: remove separate_prolog arg from prolog/epilog buildQiang Yu5-21/+13
It's always true. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24443>
2023-08-16aco: skip scratch init when no scratch arg provideQiang Yu1-17/+21
epilog does not use scratch so has no scratch arg. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
2023-08-16aco: don't emit s_endpgm for tcs with epilogQiang Yu5-10/+19
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
2023-08-16aco: add tcs epilog generation for radeonsiQiang Yu2-3/+229
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-29 16:43:51 +0000