diff options
Diffstat (limited to 'lib/Target/R600/SISchedule.td')
| -rw-r--r-- | lib/Target/R600/SISchedule.td | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/lib/Target/R600/SISchedule.td b/lib/Target/R600/SISchedule.td index d42c2e0805..5dab9511c3 100644 --- a/lib/Target/R600/SISchedule.td +++ b/lib/Target/R600/SISchedule.td @@ -32,7 +32,15 @@ def WriteIntMUL : SchedWrite; def WriteConversion : SchedWrite; def WriteI24 : SchedWrite; -def SIModel : SchedMachineModel; +def SIModel : SchedMachineModel { + int IssueWidth = 1; // Max micro-ops that may be scheduled per cycle. + int MinLatency = -1; // Determines which instructions are allowed in a group. + // (-1) inorder (0) ooo, (1): inorder +var latencies. + int MicroOpBufferSize = 0; // Max micro-ops that can be buffered. + int LoadLatency = -1; // Cycles for loads to access the cache. + int HighLatency = -1; // Approximation of cycles for "high latency" ops. + int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. +} @@ -41,10 +49,10 @@ let BufferSize = 0 in { // XXX: Are the resource counts correct? def HWBranch : ProcResource<1>; -def HWExport : ProcResource<7>; // Taken from S_WAITCNT -def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT +def HWExport : ProcResource<8>; +def HWLGKM : ProcResource<8>; def HWSALU : ProcResource<1>; -def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT +def HWVMEM : ProcResource<8>; def HWVALU : ProcResource<1>; } @@ -62,12 +70,12 @@ class HWVALUWriteRes<SchedWrite write, int latency> : // The latency numbers are taken from AMD Accelerated Parallel Processing // guide. They may not be acurate. -def : HWWriteRes<WriteBranch, [HWBranch], 100>; // XXX: Guessed ??? -def : HWWriteRes<WriteExport, [HWExport], 100>; // XXX: Guessed ??? -def : HWWriteRes<WriteLDS, [HWLGKM], 32>; // 2 - 64 -def : HWWriteRes<WriteSALU, [HWSALU], 1>; -def : HWWriteRes<WriteSMEM, [HWLGKM], 10>; // XXX: Guessed ??? -def : HWWriteRes<WriteVMEM, [HWVMEM], 450>; // 300 - 600 +def : HWWriteRes<WriteBranch, [HWBranch], 16>; +def : HWWriteRes<WriteExport, [HWExport], 200>; +def : HWWriteRes<WriteLDS, [HWLGKM], 20>; +def : HWWriteRes<WriteSALU, [HWSALU], 1>; +def : HWWriteRes<WriteSMEM, [HWLGKM], 200>; +def : HWWriteRes<WriteVMEM, [HWVMEM], 200>; // XXX: These definitions assume full double-precision speed, some devices are // slower. These are also taken from the AMD Accelerated Parallel Processing |