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//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
/// \file
//===----------------------------------------------------------------------===//
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#define MAX_LANES 64
using namespace llvm;
// Pin the vtable to this file.
void SIMachineFunctionInfo::anchor() {}
SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
: AMDGPUMachineFunction(MF),
SpillTIDVirtualReg(AMDGPU::NoRegister),
PSInputAddr(0),
SpillTracker(),
LDSWaveSpillSize(0) { }
static unsigned createLaneVGPR(MachineRegisterInfo &MRI) {
return MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
}
unsigned SIMachineFunctionInfo::RegSpillTracker::reserveLanes(
MachineRegisterInfo &MRI, unsigned NumRegs) {
unsigned StartLane = CurrentLane;
if (!LaneVGPR) {
LaneVGPR = createLaneVGPR(MRI);
} else {
CurrentLane += NumRegs;
if (CurrentLane >= MAX_LANES) {
StartLane = CurrentLane = 0;
LaneVGPR = createLaneVGPR(MRI);
} else {
StartLane++;
}
}
return StartLane;
}
void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
unsigned Reg,
int Lane) {
SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
}
const SIMachineFunctionInfo::SpilledReg&
SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) {
return SpilledRegisters[FrameIndex];
}
unsigned SIMachineFunctionInfo::getSpillTIDVirtualReg(
MachineRegisterInfo &MRI) {
if (SpillTIDVirtualReg == AMDGPU::NoRegister)
SpillTIDVirtualReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
return SpillTIDVirtualReg;
}
unsigned SIMachineFunctionInfo::allocateLDSSpaceForSpill(unsigned FrameIndex,
unsigned NumBytes) {
if (!LDSSpillOffsets.count(FrameIndex)) {
LDSSpillOffsets[FrameIndex] = LDSWaveSpillSize;
LDSWaveSpillSize += NumBytes;
}
return LDSSpillOffsets[FrameIndex];
}
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