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unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;
enum AMDILTblgenOpcode {
NONE = 0,
FEQ = 1,
FGE = 2,
FLT = 3,
FNE = 4,
MOVE_f32 = 5,
MOVE_i32 = 6,
FTOI = 7,
ITOF = 8,
CMOVLOG_f32 = 9,
UGT = 10,
IGE = 11,
INE = 12,
UGE = 13,
IEQ = 14,
AND_i32 = 15,
SMAX_i32 = 16,
CMOVLOG_Y_i32 = 17,
CMOVLOG_Z_i32 = 18,
CMOVLOG_W_i32 = 19,
SMUL_i32 = 20,
SMULHI_i32 = 21,
SHL_i32 = 22,
SHR_i32 = 23,
SHLVEC_i32 = 24,
SHRVEC_i32 = 25,
ADD_i32 = 26,
CUSTOM_XOR_i32 = 27,
CUSTOM_ADD_i32 = 28,
EADD_i32 = 29,
INTTOANY_i32 = 30,
UMUL_i32 = 31,
UMULHI_i32 = 32,
USHR_i32 = 33,
USHRVEC_i32 = 34,
UDIV_i32 = 35,
MUL_IEEE_f32 = 36,
ADD_f32 = 37,
ABS_f32 = 38,
FRAC_f32 = 39,
PIREDUCE_f32 = 40,
ROUND_NEAREST_f32 = 41,
ROUND_NEGINF_f32 = 42,
ROUND_POSINF_f32 = 43,
ROUND_ZERO_f32 = 44,
ACOS_f32 = 45,
ATAN_f32 = 46,
ASIN_f32 = 47,
TAN_f32 = 48,
SIN_f32 = 49,
COS_f32 = 50,
SQRT_f32 = 51,
EXP_f32 = 52,
EXPVEC_f32 = 53,
SQRTVEC_f32 = 54,
COSVEC_f32 = 55,
SINVEC_f32 = 56,
LOGVEC_f32 = 57,
RSQVEC_f32 = 58,
EXN_f32 = 59,
SIGN_f32 = 60,
LENGTH_f32 = 61,
POW_f32 = 62,
MIN_f32 = 63,
MAX_f32 = 64,
MAD_f32 = 65,
LN_f32 = 66,
LOG_f32 = 67,
RSQ_f32 = 68,
DIV_f32 = 69,
CLAMP_f32 = 70,
FMA_f32 = 71,
LERP_f32 = 72,
NEG_f32 = 73,
INTTOANY_f32 = 74,
UAVARENALOAD_i32 = 75,
UAVARENALOAD_Y_i32 = 76,
UAVARENALOAD_Z_i32 = 77,
UAVARENALOAD_W_i32 = 78,
UAVRAWLOAD_i32 = 79,
UAVRAWLOADCACHED_i32 = 80,
UAVARENASTORE_i32 = 81,
UAVARENASTORE_Y_i32 = 82,
UAVARENASTORE_Z_i32 = 83,
UAVARENASTORE_W_i32 = 84,
UAVRAWSTORE_i32 = 85,
GET_PRINTF_OFFSET_i32 = 86,
GET_PRINTF_SIZE_i32 = 87
};
enum AMDGPUGen {
R600_CAYMAN = 0,
R600 = 1,
EG = 2,
EG_CAYMAN = 3,
CAYMAN = 4,
SI = 5
};
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