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//===-- R600AllocateMemoryRegs.cpp - Indirect Adressing Support -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Instruction can use indirect addressing to index the register file as if it
// were memory. In order to make this work correctly we need add all registers
// that might be used for indirect addressing to the LiveIn lists of basic
// blocks and also add them as implicit uses for instructions that do
// indirect reads.
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "R600InstrInfo.h"
#include "R600MachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
namespace {
class R600AllocateMemoryRegsPass : public MachineFunctionPass {
private:
static char ID;
const R600InstrInfo *TII;
public:
R600AllocateMemoryRegsPass(TargetMachine &tm) :
MachineFunctionPass(ID),
TII(static_cast<const R600InstrInfo*>(tm.getInstrInfo()))
{ }
virtual bool runOnMachineFunction(MachineFunction &MF);
const char *getPassName() const { return "R600 Handle indirect addressing"; }
};
} // End anonymous namespace
char R600AllocateMemoryRegsPass::ID = 0;
FunctionPass *llvm::createR600AllocateMemoryRegsPass(TargetMachine &tm) {
return new R600AllocateMemoryRegsPass(tm);
}
bool R600AllocateMemoryRegsPass::runOnMachineFunction(MachineFunction &MF) {
std::vector<unsigned> IndirectRegs = TII->getIndirectReservedRegs(MF);
MachineRegisterInfo &MRI = MF.getRegInfo();
unsigned IndirectRegOffset = TII->getIndirectIndexBegin(MF);
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
I != MBB.end(); I = Next) {
Next = llvm::next(I);
MachineInstr &MI = *I;
switch (MI.getOpcode()) {
default: continue;
case AMDGPU::RegisterStore_i32:
case AMDGPU::RegisterStore_f32:
{
int64_t Offset = (MI.getOperand(2).getImm() * 4) +
MI.getOperand(3).getImm() +
(IndirectRegOffset * 4);
unsigned DstReg = AMDGPU::R600_TReg32RegClass.getRegister(Offset);
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
MFI->IndirectChannels.set(MI.getOperand(3).getImm());
if (MI.getOperand(1).getReg() == AMDGPU::ZERO) {
MFI->ReservedRegs.push_back(DstReg);
TII->buildDefaultInstruction(*BB, I, AMDGPU::MOV, DstReg,
MI.getOperand(0).getReg());
} else {
MachineInstr *MOVA = TII->buildDefaultInstruction(*BB, I,
AMDGPU::MOVA_INT_eg,
AMDGPU::AR_X,
MI.getOperand(1).getReg());
TII->setImmOperand(MOVA, R600Operands::WRITE, 0);
unsigned OffsetReg = AMDGPU::R600_AddrRegClass.getRegister(Offset);
MachineInstrBuilder MIBuilder = TII->buildDefaultInstruction(*BB, I,
AMDGPU::StackMOV, OffsetReg,
MI.getOperand(0).getReg());
MachineInstr *NewMI = MIBuilder.addReg(AMDGPU::AR_X, RegState::Implicit);
TII->setImmOperand(NewMI, R600Operands::DST_REL, 1);
}
break;
}
case AMDGPU::RegisterLoad_i32:
case AMDGPU::RegisterLoad_f32:
{
unsigned Channel = MI.getOperand(3).getImm();
unsigned Offset = (MI.getOperand(2).getImm() * 4) + Channel +
(IndirectRegOffset * 4);
unsigned OffsetReg;
if (MI.getOperand(1).getReg() == AMDGPU::ZERO) {
OffsetReg = AMDGPU::R600_TReg32RegClass.getRegister(Offset);
TII->buildDefaultInstruction(MBB, I, AMDGPU::MOV,
MI.getOperand(0).getReg(),
OffsetReg);
} else {
R600MachineFunctionInfo * MFI = MF.getInfo<R600MachineFunctionInfo>();
MachineInstr *MOVA = TII->buildDefaultInstruction(*BB, I,
AMDGPU::MOVA_INT_eg,
AMDGPU::AR_X,
MI.getOperand(1).getReg());
TII->setImmOperand(MOVA, R600Operands::WRITE, 0);
OffsetReg = AMDGPU::R600_AddrRegClass.getRegister(Offset);
MachineInstrBuilder MIBuilder = TII->buildDefaultInstruction(*BB, I,
AMDGPU::MOV, MI.getOperand(0).getReg(),
OffsetReg);
for (std::vector<unsigned>::iterator RRI = MFI->ReservedRegs.begin(),
RRE = MFI->ReservedRegs.end();
RRE != RRI; ++RRI) {
unsigned Reg = *RRI;
if (GET_REG_CHAN(Reg) == Channel) {
MIBuilder.addReg(Reg, RegState::Implicit);
}
}
MachineInstr *NewMI = MIBuilder.addReg(AMDGPU::AR_X, RegState::Implicit);
TII->setImmOperand(NewMI, R600Operands::SRC0_REL, 1);
}
break;
}
}
MI.eraseFromParent();
}
}
return false;
}
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