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//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
/// \file
/// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
//
//===----------------------------------------------------------------------===//
#include "AMDGPURegisterInfo.h"
#include "AMDGPUTargetMachine.h"
using namespace llvm;
AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
const TargetInstrInfo &tii)
: AMDGPUGenRegisterInfo(0),
TM(tm),
TII(tii)
{ }
//===----------------------------------------------------------------------===//
// Function handling callbacks - Functions are a seldom used feature of GPUS, so
// they are not supported at this time.
//===----------------------------------------------------------------------===//
const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
const {
return &CalleeSavedReg;
}
void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
int SPAdj,
RegScavenger *RS) const {
assert(!"Subroutines not supported yet");
}
unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
assert(!"Subroutines not supported yet");
return 0;
}
unsigned AMDGPURegisterInfo::getIndirectSubReg(unsigned IndirectIndex) const {
switch(IndirectIndex) {
case 0: return AMDGPU::indirect_0;
case 1: return AMDGPU::indirect_1;
case 2: return AMDGPU::indirect_2;
case 3: return AMDGPU::indirect_3;
case 4: return AMDGPU::indirect_4;
case 5: return AMDGPU::indirect_5;
case 6: return AMDGPU::indirect_6;
case 7: return AMDGPU::indirect_7;
case 8: return AMDGPU::indirect_8;
case 9: return AMDGPU::indirect_9;
case 10: return AMDGPU::indirect_10;
case 11: return AMDGPU::indirect_11;
case 12: return AMDGPU::indirect_12;
case 13: return AMDGPU::indirect_13;
case 14: return AMDGPU::indirect_14;
case 15: return AMDGPU::indirect_15;
case 16: return AMDGPU::indirect_16;
case 17: return AMDGPU::indirect_17;
case 18: return AMDGPU::indirect_18;
case 19: return AMDGPU::indirect_19;
case 20: return AMDGPU::indirect_20;
case 21: return AMDGPU::indirect_21;
case 22: return AMDGPU::indirect_22;
case 23: return AMDGPU::indirect_23;
case 24: return AMDGPU::indirect_24;
case 25: return AMDGPU::indirect_25;
case 26: return AMDGPU::indirect_26;
case 27: return AMDGPU::indirect_27;
case 28: return AMDGPU::indirect_28;
case 29: return AMDGPU::indirect_29;
case 30: return AMDGPU::indirect_30;
case 31: return AMDGPU::indirect_31;
case 32: return AMDGPU::indirect_32;
case 33: return AMDGPU::indirect_33;
case 34: return AMDGPU::indirect_34;
case 35: return AMDGPU::indirect_35;
case 36: return AMDGPU::indirect_36;
case 37: return AMDGPU::indirect_37;
case 38: return AMDGPU::indirect_38;
case 39: return AMDGPU::indirect_39;
case 40: return AMDGPU::indirect_40;
case 41: return AMDGPU::indirect_41;
case 42: return AMDGPU::indirect_42;
case 43: return AMDGPU::indirect_43;
case 44: return AMDGPU::indirect_44;
case 45: return AMDGPU::indirect_45;
case 46: return AMDGPU::indirect_46;
case 47: return AMDGPU::indirect_47;
case 48: return AMDGPU::indirect_48;
case 49: return AMDGPU::indirect_49;
case 50: return AMDGPU::indirect_50;
case 51: return AMDGPU::indirect_51;
case 52: return AMDGPU::indirect_52;
case 53: return AMDGPU::indirect_53;
case 54: return AMDGPU::indirect_54;
case 55: return AMDGPU::indirect_55;
case 56: return AMDGPU::indirect_56;
case 57: return AMDGPU::indirect_57;
case 58: return AMDGPU::indirect_58;
case 59: return AMDGPU::indirect_59;
case 60: return AMDGPU::indirect_60;
case 61: return AMDGPU::indirect_61;
case 62: return AMDGPU::indirect_62;
case 63: return AMDGPU::indirect_63;
#if 0
case 64: return AMDGPU::indirect_64;
case 65: return AMDGPU::indirect_65;
case 66: return AMDGPU::indirect_66;
case 67: return AMDGPU::indirect_67;
case 68: return AMDGPU::indirect_68;
case 69: return AMDGPU::indirect_69;
case 70: return AMDGPU::indirect_70;
case 71: return AMDGPU::indirect_71;
case 72: return AMDGPU::indirect_72;
case 73: return AMDGPU::indirect_73;
case 74: return AMDGPU::indirect_74;
case 75: return AMDGPU::indirect_75;
case 76: return AMDGPU::indirect_76;
case 77: return AMDGPU::indirect_77;
case 78: return AMDGPU::indirect_78;
case 79: return AMDGPU::indirect_79;
case 80: return AMDGPU::indirect_80;
case 81: return AMDGPU::indirect_81;
case 82: return AMDGPU::indirect_82;
case 83: return AMDGPU::indirect_83;
case 84: return AMDGPU::indirect_84;
case 85: return AMDGPU::indirect_85;
case 86: return AMDGPU::indirect_86;
case 87: return AMDGPU::indirect_87;
case 88: return AMDGPU::indirect_88;
case 89: return AMDGPU::indirect_89;
case 90: return AMDGPU::indirect_90;
case 91: return AMDGPU::indirect_91;
case 92: return AMDGPU::indirect_92;
case 93: return AMDGPU::indirect_93;
case 94: return AMDGPU::indirect_94;
case 95: return AMDGPU::indirect_95;
case 96: return AMDGPU::indirect_96;
case 97: return AMDGPU::indirect_97;
case 98: return AMDGPU::indirect_98;
case 99: return AMDGPU::indirect_99;
case 100: return AMDGPU::indirect_100;
case 101: return AMDGPU::indirect_101;
case 102: return AMDGPU::indirect_102;
case 103: return AMDGPU::indirect_103;
case 104: return AMDGPU::indirect_104;
case 105: return AMDGPU::indirect_105;
case 106: return AMDGPU::indirect_106;
case 107: return AMDGPU::indirect_107;
case 108: return AMDGPU::indirect_108;
case 109: return AMDGPU::indirect_109;
case 110: return AMDGPU::indirect_110;
case 111: return AMDGPU::indirect_111;
case 112: return AMDGPU::indirect_112;
case 113: return AMDGPU::indirect_113;
case 114: return AMDGPU::indirect_114;
case 115: return AMDGPU::indirect_115;
case 116: return AMDGPU::indirect_116;
case 117: return AMDGPU::indirect_117;
case 118: return AMDGPU::indirect_118;
case 119: return AMDGPU::indirect_119;
case 120: return AMDGPU::indirect_120;
case 121: return AMDGPU::indirect_121;
case 122: return AMDGPU::indirect_122;
case 123: return AMDGPU::indirect_123;
case 124: return AMDGPU::indirect_124;
case 125: return AMDGPU::indirect_125;
case 126: return AMDGPU::indirect_126;
case 127: return AMDGPU::indirect_127;
#endif
default: llvm_unreachable("indirect index out of range");
}
}
#define GET_REGINFO_TARGET_DESC
#include "AMDGPUGenRegisterInfo.inc"
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