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BranchCommit messageAuthorAge
9.1-abi-fixR600: Move intrinsic definitions into the R600 target directoryTom Stellard7 years
Nov13-testAMDGPU: Fix builds with -DNDEBUGTom Stellard7 years
Oct18-backupR600: Remove deprecated code from R600MCCodeEmitterTom Stellard7 years
assemblerXXX: Select all immediates to SALUTom Stellard5 years
assembler-Jan-06-2015XXX: R600/SI VOP1 AssemblerTom Stellard5 years
assembler-pushR600/SI: Initial support for assembler and inline assemblyTom Stellard5 years
backup-Oct15XXX: WIP no MIOperandInfo wayTom Stellard7 years
backup-Oct18R600: Organize pseudo instruction in R600Instructions.tdTom Stellard7 years
bfgminerXXX: R600: limit vtx clauses to one instructionsTom Stellard7 years
bfgminer-perfR600: Use correct CF_END instruction on Northern Island GPUsTom Stellard7 years
cayman-only-bfgminerXXX: Use correct encoding for Vertex Fetch instructions on Cayman.Tom Stellard7 years
clover-elfR600: AsmPrinter - Call EmitFunctionHeader() to populate symbol tableTom Stellard6 years
clover-elf-v2R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard5 years
hazard-recAMDGPU: Implement SIRegisterInfo::getRegPressureSetScore()Tom Stellard4 years
hsaR600/SI: Emit amd_kernel_code_t header for AMDGPU environmentTom Stellard5 years
image-supportXXX: WorkingTom Stellard7 years
indirect-addressingXXX:Tom Stellard7 years
indirect-wipXXX: Backout LiveInterval changes and don't run MachineCSETom Stellard7 years
indirect-wip-2R600: Support for indirect addressingTom Stellard7 years
indirect-wip-3XXX: First try at LDS.Tom Stellard7 years
indirect-wip-4XXX: Moved most of code into its own path using Christian's REG_SEQUENCETom Stellard7 years
indirect-wip-5R600: Support for indirect addressingTom Stellard7 years
kernel-args-WIPXXX: Kernel argsTom Stellard6 years
ldsXXX: More LDSTom Stellard7 years
lds-v2R600: Add local memory support via LDSTom Stellard7 years
long-aluXXX: Barrier squashTom Stellard6 years
madkR600/SI: Use v_madmk_f32Matt Arsenault5 years
masterR600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer7 years
master-testingSROA: Prevent a cross address space bitcastTom Stellard6 years
master-testing-patchesR600/SI: Use immediates offsets for SMRD instructions whenever possibleTom Stellard6 years
master-testing-patches-v2XXX: Matt's patchTom Stellard6 years
master-testing-siXXX: Const fixesTom Stellard6 years
master-testing-v2XXX: 32-bit priv fixesTom Stellard6 years
mi-sched-experimentalScheduleDAGInstrs: Consider sub-registers when computing vreg def dependenciesTom Stellard5 years
nativeR600: use native for aluVincent Lejeune7 years
opencv-Sep18-patchesStructurizeCFG: Add dependency on LowerSwitch passTom Stellard6 years
perf-Dec31-2014R600: Enable subreg livenessTom Stellard5 years
perf-Jan-08-2015R600: Enable subreg livenessTom Stellard5 years
push-jan16R600/SI: Use unnormalized coordinates for sampling with the RECT target.Michel Dänzer7 years
r600test/CodeGen/R600: Add some basic testsTom Stellard8 years
r600-May09R600: Remove R600ShaderPatterns.tdTom Stellard8 years
r600-alu-encodingR600: Remove deprecated code from R600MCCodeEmitterTom Stellard7 years
r600-final-pushFix warningsTom Stellard8 years
r600-gen-fixesR600: Fix the fetch limits for R600 generation GPUsTom Stellard7 years
r600-imm-flagsAMDGPU: Use new OperandWithDefaultOps for DOT* instructionsTom Stellard7 years
r600-initial-reviewBuild script changes for R600/SI CodegenTom Stellard8 years
r600-initial-review-May11Fixup SIInstrInfo after patchesTom Stellard8 years
r600-mastertest/CodeGen/R600: Add some basic tests v7Tom Stellard8 years
r600-private-mem-fixesR600/SI: Add support for private address space load/storeTom Stellard6 years
r600-private-memoryXXX: SALUTom Stellard6 years
r600-review-v10R600: Fix lowering of vbuildTom Stellard7 years
r600-review-v3AMDIL: Add missing files R600MachineFunctionInfo.{cpp,h}Tom Stellard8 years
r600-review-v7test/CodeGen/R600: Add some basic testsTom Stellard7 years
r600-review-v8test/CodeGen/R600: Add some basic testsTom Stellard7 years
r600-review-v9AMDGPU: Fix register assembly for SITom Stellard7 years
r600-rewrite-patsR600: Convert the rest of the patternsTom Stellard7 years
r600-structurizerXXX: Fix failure of assrtTom Stellard7 years
r600-structurizer-v2XXX: Lower PRED_SET directly to PRED_SET_*Tom Stellard7 years
r600-tablegen-hwregAdd MCRegisterInfo parameter to createMCCodeEmitter functionsTom Stellard8 years
r600-tablegen-reg-encodingAMDIL: Remove SubRegClasses field from Register ClassesTom Stellard8 years
r600-vliwAMDIL: Add AMDGPUSubtarget classTom Stellard8 years
remove-fold-operandsR600/SI: Remove SIISelLowering::legalizeOperands()Tom Stellard5 years
sched-fixesXXX: Indirect fixesTom Stellard7 years
sched-perf-Mar-27-2015R600/SI: Disable register pressure tracking in the schedulerTom Stellard5 years
si-computeXXX: It worksTom Stellard7 years
si-compute-v3XXX: Add real SI processorsTom Stellard7 years
si-foldR600/SI: Add SIFoldOperands passTom Stellard5 years
si-lowercaseR600/SI: Change all instruction assembly names to lowercase.Tom Stellard5 years
si-schedulerR600/SI: Define a schedule model and enable the converging schedulerTom Stellard6 years
si-scheduler-v2R600/SI: Define a schedule model and enable the generic machine schedulerTom Stellard6 years
si-scheduler-v3R600/SI: Define a schedule model and enable the generic machine schedulerTom Stellard5 years
si-sgpr-copiesR600/SI: Use VSrc_* register classes as the default classes for typesTom Stellard7 years
si-spill-fixesR600/SI: Implement VGPR register spillingTom Stellard6 years
si-spill-fixes-v2R600/SI: XXX: Use correct operands for DS instructionsTom Stellard6 years
si-spill-fixes-v3R600/SI: Implement VGPR register spilling v2Tom Stellard6 years
si-spill-fixes-v4R600/SI: Implement VGPR register spilling v2Tom Stellard6 years
smrd-clusterR600/SI: Enable post-ra machine schedulerTom Stellard5 years
struct-divergenceXXX: remove debug prints.Tom Stellard4 years
struct-divergence-v1XXX: Struct fixesTom Stellard4 years
vgpr-spilling-Jan07-2014XXX: Clear some kill flags.Tom Stellard5 years
vinterp-fixR600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard5 years
vliw5-rebaseR600: Support schedule and packetization of trans-only instVincent Lejeune7 years
vlj-bottom-upgroup idother instVincent Lejeune7 years
 
TagDownloadAuthorAge
mesa-9.1.1commit ce7bbb8b46...Michel Danzer7 years
mesa-9.1commit 16ca877f58...Michel Danzer7 years