From 32a8be2a172081714d9e15f7551bc381ae656126 Mon Sep 17 00:00:00 2001
From: tstellar <tstellar@91177308-0d34-0410-b5e6-96231b3b80d8>
Date: Tue, 9 Oct 2012 18:49:02 +0000
Subject: R600: Add a pattern for:  (selectcc i32, -1, i32, i32, SETGT)

This is now lowered to a CNDGE_INT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165525 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AMDGPU/R600Instructions.td | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'lib/Target')

diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 2cf5fcae1e3..6da756215e7 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -1377,6 +1377,13 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
 // ISel Patterns
 //===----------------------------------------------------------------------===//
 
+//CNDGE_INT extra pattern
+def : Pat <
+  (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
+                                        (i32 R600_Reg32:$src2), COND_GT),
+  (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
+>;
+
 // KIL Patterns
 def KILP : Pat <
   (int_AMDGPU_kilp),
-- 
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