From 831c5c82f3fc1899e51d1bd976587f4c2b4ef84f Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 8 Oct 2012 15:37:39 +0200 Subject: R600: Use native operands for R600_1OP instructions --- lib/Target/AMDGPU/R600RegisterInfo.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/Target/AMDGPU/R600RegisterInfo.td') diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td b/lib/Target/AMDGPU/R600RegisterInfo.td index 58c6c3564cf..c682f2bf09f 100644 --- a/lib/Target/AMDGPU/R600RegisterInfo.td +++ b/lib/Target/AMDGPU/R600RegisterInfo.td @@ -53,8 +53,8 @@ def ALU_LITERAL_X : R600Reg<"literal.x", 253>; def PV_X : R600Reg<"pv.x", 254>; def PREDICATE_BIT : R600Reg<"PredicateBit", 0>; def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>; -def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 0>; -def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 0>; +def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>; +def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>; def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add (interleave -- cgit v1.2.3