From 3cfa231f802b9ea294c847ec893964a01fc601d6 Mon Sep 17 00:00:00 2001 From: tstellar Date: Tue, 2 Oct 2012 14:15:43 +0000 Subject: R600: Fix instruction encoding for r600 family GPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested-by: Michel Dänzer https://bugs.freedesktop.org/show_bug.cgi?id=55217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165012 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp') diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp index 274400aa34a..0ef0a9c2ad7 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp @@ -216,8 +216,8 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI, //older alu have different encoding for instructions with one or two src //parameters. - if (STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst && - MI.getNumOperands() < 4) { + if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && + !(MCDesc.TSFlags & R600_InstFlag::OP3)) { uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39); InstWord01 &= ~(0x3FFULL << 39); InstWord01 |= ISAOpCode << 1; -- cgit v1.2.3